SSPP_VIG1         190 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 	SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SDM845_MASK,
SSPP_VIG1         124 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 	case SSPP_VIG1:
SSPP_VIG1         334 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 			case SSPP_VIG1:
SSPP_VIG1         380 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 	{ DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG1, DPU_INTR_HIST_VIG_1_DONE, 2},
SSPP_VIG1         381 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 	{ DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG1,
SSPP_VIG1         140 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c 	status->sspp[SSPP_VIG1] = (value >> 6) & 0x3;
SSPP_VIG1         237 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c 	status->sspp[SSPP_VIG1] = (value >> 6) & 0x1;
SSPP_VIG1         540 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h 		case SSPP_VIG1: return (mdp5_cfg->pipe_vig.base[1]);
SSPP_VIG1          28 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 			[SSPP_VIG0] =  1, [SSPP_VIG1] =  4, [SSPP_VIG2] =  7,
SSPP_VIG1         112 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 			[SSPP_VIG0] =  1, [SSPP_VIG1] =  4, [SSPP_VIG2] =  7,
SSPP_VIG1         195 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 			[SSPP_VIG0] =  1, [SSPP_VIG1] =  4,
SSPP_VIG1         357 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 			[SSPP_VIG0] =  1, [SSPP_VIG1] =  4,
SSPP_VIG1         291 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	case SSPP_VIG1: return MDP5_CTL_LAYER_REG_VIG1(stage);
SSPP_VIG1         314 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	case SSPP_VIG1: return MDP5_CTL_LAYER_EXT_REG_VIG1_BIT3;
SSPP_VIG1         442 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	case SSPP_VIG1: return MDP5_CTL_FLUSH_VIG1;
SSPP_VIG1         831 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 			SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3,