SSPP_VIG0         146 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 				dpu_plane_pipe(plane) - SSPP_VIG0,
SSPP_VIG0         162 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 					   dpu_plane_pipe(plane) - SSPP_VIG0,
SSPP_VIG0         188 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 	SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SDM845_MASK,
SSPP_VIG0         121 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 	case SSPP_VIG0:
SSPP_VIG0         326 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 			case SSPP_VIG0:
SSPP_VIG0         374 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 	{ DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG0, DPU_INTR_HIST_VIG_0_DONE, 2},
SSPP_VIG0         375 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 	{ DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG0,
SSPP_VIG0         139 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c 	status->sspp[SSPP_VIG0] = (value >> 4) & 0x3;
SSPP_VIG0         236 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c 	status->sspp[SSPP_VIG0] = (value >> 4) & 0x1;
SSPP_VIG0          99 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c 	for (i = SSPP_VIG0; i < SSPP_MAX; i++)
SSPP_VIG0         100 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c 		seq_printf(s, "SSPP%d   :  0x%x  \t", i - SSPP_VIG0,
SSPP_VIG0         185 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			plane->base.id, pdpu->pipe - SSPP_VIG0,
SSPP_VIG0         250 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	trace_dpu_perf_set_qos_luts(pdpu->pipe - SSPP_VIG0,
SSPP_VIG0         256 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			pdpu->pipe - SSPP_VIG0,
SSPP_VIG0         301 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0,
SSPP_VIG0         309 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pdpu->pipe - SSPP_VIG0,
SSPP_VIG0         353 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pdpu->pipe - SSPP_VIG0,
SSPP_VIG0         404 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	qos_params.num = pdpu->pipe_hw->idx - SSPP_VIG0;
SSPP_VIG0         539 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h 		case SSPP_VIG0: return (mdp5_cfg->pipe_vig.base[0]);
SSPP_VIG0          28 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 			[SSPP_VIG0] =  1, [SSPP_VIG1] =  4, [SSPP_VIG2] =  7,
SSPP_VIG0         112 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 			[SSPP_VIG0] =  1, [SSPP_VIG1] =  4, [SSPP_VIG2] =  7,
SSPP_VIG0         195 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 			[SSPP_VIG0] =  1, [SSPP_VIG1] =  4,
SSPP_VIG0         290 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 			[SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
SSPP_VIG0         357 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 			[SSPP_VIG0] =  1, [SSPP_VIG1] =  4,
SSPP_VIG0         290 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	case SSPP_VIG0: return MDP5_CTL_LAYER_REG_VIG0(stage);
SSPP_VIG0         313 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	case SSPP_VIG0: return MDP5_CTL_LAYER_EXT_REG_VIG0_BIT3;
SSPP_VIG0         441 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	case SSPP_VIG0: return MDP5_CTL_FLUSH_VIG0;
SSPP_VIG0         831 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 			SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3,