SSPP_RGB2         139 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 	case SSPP_RGB2:
SSPP_RGB2         366 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 			case SSPP_RGB2:
SSPP_RGB2         145 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c 	status->sspp[SSPP_RGB2] = (value >> 16) & 0x3;
SSPP_RGB2         242 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c 	status->sspp[SSPP_RGB2] = (value >> 16) & 0x1;
SSPP_RGB2         544 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h 		case SSPP_RGB2: return (mdp5_cfg->pipe_rgb.base[2]);
SSPP_RGB2          30 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 			[SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
SSPP_RGB2         114 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 			[SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
SSPP_RGB2         199 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 			[SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
SSPP_RGB2         361 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 			[SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
SSPP_RGB2         295 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	case SSPP_RGB2: return MDP5_CTL_LAYER_REG_RGB2(stage);
SSPP_RGB2         318 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	case SSPP_RGB2: return MDP5_CTL_LAYER_EXT_REG_RGB2_BIT3;
SSPP_RGB2         446 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	case SSPP_RGB2: return MDP5_CTL_FLUSH_RGB2;
SSPP_RGB2         828 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 			SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3,
SSPP_RGB2         213 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h 	case SSPP_RGB2: