SSPP_RGB1 136 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c case SSPP_RGB1: SSPP_RGB1 362 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c case SSPP_RGB1: SSPP_RGB1 144 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c status->sspp[SSPP_RGB1] = (value >> 14) & 0x3; SSPP_RGB1 241 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c status->sspp[SSPP_RGB1] = (value >> 14) & 0x1; SSPP_RGB1 543 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case SSPP_RGB1: return (mdp5_cfg->pipe_rgb.base[1]); SSPP_RGB1 30 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c [SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18, SSPP_RGB1 114 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c [SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18, SSPP_RGB1 198 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c [SSPP_RGB0] = 16, [SSPP_RGB1] = 17, SSPP_RGB1 291 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c [SSPP_RGB0] = 7, [SSPP_RGB1] = 8, SSPP_RGB1 360 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c [SSPP_RGB0] = 16, [SSPP_RGB1] = 17, SSPP_RGB1 294 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c case SSPP_RGB1: return MDP5_CTL_LAYER_REG_RGB1(stage); SSPP_RGB1 317 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c case SSPP_RGB1: return MDP5_CTL_LAYER_EXT_REG_RGB1_BIT3; SSPP_RGB1 445 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c case SSPP_RGB1: return MDP5_CTL_FLUSH_RGB1; SSPP_RGB1 828 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3, SSPP_RGB1 212 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h case SSPP_RGB1: