SSPP_RGB0         133 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 	case SSPP_RGB0:
SSPP_RGB0         358 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 			case SSPP_RGB0:
SSPP_RGB0         143 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c 	status->sspp[SSPP_RGB0] = (value >> 12) & 0x3;
SSPP_RGB0         240 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c 	status->sspp[SSPP_RGB0] = (value >> 12) & 0x1;
SSPP_RGB0         542 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h 		case SSPP_RGB0: return (mdp5_cfg->pipe_rgb.base[0]);
SSPP_RGB0          30 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 			[SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
SSPP_RGB0         114 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 			[SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
SSPP_RGB0         198 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 			[SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
SSPP_RGB0         291 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 			[SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
SSPP_RGB0         360 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 			[SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
SSPP_RGB0         293 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	case SSPP_RGB0: return MDP5_CTL_LAYER_REG_RGB0(stage);
SSPP_RGB0         316 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	case SSPP_RGB0: return MDP5_CTL_LAYER_EXT_REG_RGB0_BIT3;
SSPP_RGB0         444 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	case SSPP_RGB0: return MDP5_CTL_FLUSH_RGB0;
SSPP_RGB0         828 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 			SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3,
SSPP_RGB0         211 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h 	case SSPP_RGB0: