SSPP_MAX          826 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 	const struct drm_plane_state *pipe_staged[SSPP_MAX];
SSPP_MAX          904 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 	for (i = 1; i < SSPP_MAX; i++) {
SSPP_MAX          676 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c 	if ((sspp < SSPP_MAX) && catalog && addr && b) {
SSPP_MAX           53 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h 	u8 sspp[SSPP_MAX];
SSPP_MAX           99 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c 	for (i = SSPP_VIG0; i < SSPP_MAX; i++)
SSPP_MAX           28 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h 	struct mdp5_hw_pipe *hwpipes[SSPP_MAX];
SSPP_MAX           33 drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.h 	struct drm_plane *hwpipe_to_plane[SSPP_MAX];
SSPP_MAX           26 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c 	u32 pipe_reqprio_fifo_wm0[SSPP_MAX];
SSPP_MAX           27 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c 	u32 pipe_reqprio_fifo_wm1[SSPP_MAX];
SSPP_MAX           28 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c 	u32 pipe_reqprio_fifo_wm2[SSPP_MAX];