SSPP_DMA1 198 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, SSPP_DMA1 148 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c case SSPP_DMA1: SSPP_DMA1 382 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c case SSPP_DMA1: SSPP_DMA1 148 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c status->sspp[SSPP_DMA1] = (value >> 22) & 0x3; SSPP_DMA1 245 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c status->sspp[SSPP_DMA1] = (value >> 22) & 0x1; SSPP_DMA1 546 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case SSPP_DMA1: return (mdp5_cfg->pipe_dma.base[1]); SSPP_DMA1 29 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c [SSPP_DMA0] = 10, [SSPP_DMA1] = 13, SSPP_DMA1 113 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c [SSPP_DMA0] = 10, [SSPP_DMA1] = 13, SSPP_DMA1 197 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c [SSPP_DMA0] = 10, [SSPP_DMA1] = 13, SSPP_DMA1 359 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c [SSPP_DMA0] = 10, [SSPP_DMA1] = 13, SSPP_DMA1 297 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c case SSPP_DMA1: return MDP5_CTL_LAYER_REG_DMA1(stage); SSPP_DMA1 320 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c case SSPP_DMA1: return MDP5_CTL_LAYER_EXT_REG_DMA1_BIT3; SSPP_DMA1 448 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c case SSPP_DMA1: return MDP5_CTL_FLUSH_DMA1; SSPP_DMA1 834 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c SSPP_DMA0, SSPP_DMA1,