SSPP_DMA0         196 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 	SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000,  DMA_SDM845_MASK,
SSPP_DMA0         145 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 	case SSPP_DMA0:
SSPP_DMA0         374 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 			case SSPP_DMA0:
SSPP_DMA0         147 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c 	status->sspp[SSPP_DMA0] = (value >> 20) & 0x3;
SSPP_DMA0         244 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c 	status->sspp[SSPP_DMA0] = (value >> 20) & 0x1;
SSPP_DMA0         545 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h 		case SSPP_DMA0: return (mdp5_cfg->pipe_dma.base[0]);
SSPP_DMA0          29 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 			[SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
SSPP_DMA0         113 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 			[SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
SSPP_DMA0         197 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 			[SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
SSPP_DMA0         290 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 			[SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
SSPP_DMA0         359 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 			[SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
SSPP_DMA0         296 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	case SSPP_DMA0: return MDP5_CTL_LAYER_REG_DMA0(stage);
SSPP_DMA0         319 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	case SSPP_DMA0: return MDP5_CTL_LAYER_EXT_REG_DMA0_BIT3;
SSPP_DMA0         447 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	case SSPP_DMA0: return MDP5_CTL_FLUSH_DMA0;
SSPP_DMA0         834 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 			SSPP_DMA0, SSPP_DMA1,