SSPP_CURSOR1 160 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c case SSPP_CURSOR1: SSPP_CURSOR1 409 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c case SSPP_CURSOR1: SSPP_CURSOR1 152 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c status->sspp[SSPP_CURSOR1] = (value >> 26) & 0x3; SSPP_CURSOR1 249 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c status->sspp[SSPP_CURSOR1] = (value >> 26) & 0x1; SSPP_CURSOR1 550 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case SSPP_CURSOR1: return (mdp5_cfg->pipe_cursor.base[1]); SSPP_CURSOR1 301 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c case SSPP_CURSOR1: SSPP_CURSOR1 309 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c if (stage < STAGE6 && (pipe != SSPP_CURSOR0 && pipe != SSPP_CURSOR1)) SSPP_CURSOR1 324 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c case SSPP_CURSOR1: return MDP5_CTL_LAYER_EXT_REG_CURSOR1(stage); SSPP_CURSOR1 452 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c case SSPP_CURSOR1: return MDP5_CTL_FLUSH_CURSOR_1; SSPP_CURSOR1 837 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c SSPP_CURSOR0, SSPP_CURSOR1, SSPP_CURSOR1 11 drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.h #define SSPP_MAX (SSPP_CURSOR1 + 1)