SSPP_CURSOR0      157 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 	case SSPP_CURSOR0:
SSPP_CURSOR0      406 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 			case SSPP_CURSOR0:
SSPP_CURSOR0      151 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c 	status->sspp[SSPP_CURSOR0] = (value >> 24) & 0x3;
SSPP_CURSOR0      248 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c 	status->sspp[SSPP_CURSOR0] = (value >> 24) & 0x1;
SSPP_CURSOR0      549 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h 		case SSPP_CURSOR0: return (mdp5_cfg->pipe_cursor.base[0]);
SSPP_CURSOR0      300 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	case SSPP_CURSOR0:
SSPP_CURSOR0      309 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	if (stage < STAGE6 && (pipe != SSPP_CURSOR0 && pipe != SSPP_CURSOR1))
SSPP_CURSOR0      323 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	case SSPP_CURSOR0: return MDP5_CTL_LAYER_EXT_REG_CURSOR0(stage);
SSPP_CURSOR0      451 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	case SSPP_CURSOR0: return MDP5_CTL_FLUSH_CURSOR_0;
SSPP_CURSOR0      837 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 			SSPP_CURSOR0, SSPP_CURSOR1,