SRII 61 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PHASE, DP_DTO, 0),\ SRII 62 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PHASE, DP_DTO, 1),\ SRII 63 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PHASE, DP_DTO, 2),\ SRII 64 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PHASE, DP_DTO, 3),\ SRII 65 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PHASE, DP_DTO, 4),\ SRII 66 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PHASE, DP_DTO, 5),\ SRII 67 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(MODULO, DP_DTO, 0),\ SRII 68 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(MODULO, DP_DTO, 1),\ SRII 69 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(MODULO, DP_DTO, 2),\ SRII 70 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(MODULO, DP_DTO, 3),\ SRII 71 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(MODULO, DP_DTO, 4),\ SRII 72 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(MODULO, DP_DTO, 5),\ SRII 73 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PIXEL_RATE_CNTL, OTG, 0),\ SRII 74 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PIXEL_RATE_CNTL, OTG, 1),\ SRII 75 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PIXEL_RATE_CNTL, OTG, 2),\ SRII 76 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PIXEL_RATE_CNTL, OTG, 3),\ SRII 77 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PIXEL_RATE_CNTL, OTG, 4),\ SRII 78 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PIXEL_RATE_CNTL, OTG, 5) SRII 84 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PHASE, DP_DTO, 0),\ SRII 85 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PHASE, DP_DTO, 1),\ SRII 86 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PHASE, DP_DTO, 2),\ SRII 87 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PHASE, DP_DTO, 3),\ SRII 88 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(MODULO, DP_DTO, 0),\ SRII 89 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(MODULO, DP_DTO, 1),\ SRII 90 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(MODULO, DP_DTO, 2),\ SRII 91 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(MODULO, DP_DTO, 3),\ SRII 92 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PIXEL_RATE_CNTL, OTG, 0),\ SRII 93 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PIXEL_RATE_CNTL, OTG, 1),\ SRII 94 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PIXEL_RATE_CNTL, OTG, 2),\ SRII 95 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PIXEL_RATE_CNTL, OTG, 3) SRII 110 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PHASE, DP_DTO, 0),\ SRII 111 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PHASE, DP_DTO, 1),\ SRII 112 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PHASE, DP_DTO, 2),\ SRII 113 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PHASE, DP_DTO, 3),\ SRII 114 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(MODULO, DP_DTO, 0),\ SRII 115 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(MODULO, DP_DTO, 1),\ SRII 116 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(MODULO, DP_DTO, 2),\ SRII 117 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(MODULO, DP_DTO, 3),\ SRII 118 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PIXEL_RATE_CNTL, OTG, 0), \ SRII 119 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PIXEL_RATE_CNTL, OTG, 1), \ SRII 120 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PIXEL_RATE_CNTL, OTG, 2), \ SRII 121 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PIXEL_RATE_CNTL, OTG, 3) SRII 43 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \ SRII 44 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \ SRII 45 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \ SRII 46 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(DCFE_CLOCK_CONTROL, DCFE, 3), \ SRII 47 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(DCFE_CLOCK_CONTROL, DCFE, 4), \ SRII 48 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(DCFE_CLOCK_CONTROL, DCFE, 5), \ SRII 52 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(BLND_V_UPDATE_LOCK, BLND, 0), \ SRII 53 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(BLND_V_UPDATE_LOCK, BLND, 1), \ SRII 54 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(BLND_V_UPDATE_LOCK, BLND, 2), \ SRII 55 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(BLND_V_UPDATE_LOCK, BLND, 3), \ SRII 56 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(BLND_V_UPDATE_LOCK, BLND, 4), \ SRII 57 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(BLND_V_UPDATE_LOCK, BLND, 5), \ SRII 58 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(BLND_CONTROL, BLND, 0), \ SRII 59 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(BLND_CONTROL, BLND, 1), \ SRII 60 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(BLND_CONTROL, BLND, 2), \ SRII 61 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(BLND_CONTROL, BLND, 3), \ SRII 62 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(BLND_CONTROL, BLND, 4), \ SRII 63 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(BLND_CONTROL, BLND, 5) SRII 66 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(PIXEL_RATE_CNTL, blk, inst), \ SRII 67 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(PHYPLL_PIXEL_RATE_CNTL, blk, inst) SRII 70 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(PIXEL_RATE_CNTL, blk, 0), \ SRII 71 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(PIXEL_RATE_CNTL, blk, 1), \ SRII 72 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(PIXEL_RATE_CNTL, blk, 2), \ SRII 73 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(PIXEL_RATE_CNTL, blk, 3), \ SRII 74 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(PIXEL_RATE_CNTL, blk, 4), \ SRII 75 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(PIXEL_RATE_CNTL, blk, 5) SRII 78 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \ SRII 79 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1), \ SRII 80 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2), \ SRII 81 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \ SRII 82 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \ SRII 83 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5) SRII 88 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \ SRII 89 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \ SRII 90 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(CRTC_H_BLANK_START_END, CRTC, 0),\ SRII 91 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(CRTC_H_BLANK_START_END, CRTC, 1),\ SRII 92 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(BLND_V_UPDATE_LOCK, BLND, 0),\ SRII 93 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(BLND_V_UPDATE_LOCK, BLND, 1),\ SRII 94 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(BLND_CONTROL, BLND, 0),\ SRII 95 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(BLND_CONTROL, BLND, 1),\ SRII 121 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \ SRII 122 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(CRTC_H_BLANK_START_END, CRTC, 2), \ SRII 123 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(BLND_V_UPDATE_LOCK, BLND, 2), \ SRII 124 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SRII(BLND_CONTROL, BLND, 2), \ SRII 34 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SRII(MPCC_TOP_SEL, MPCC, inst),\ SRII 35 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SRII(MPCC_BOT_SEL, MPCC, inst),\ SRII 36 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SRII(MPCC_CONTROL, MPCC, inst),\ SRII 37 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SRII(MPCC_STATUS, MPCC, inst),\ SRII 38 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SRII(MPCC_OPP_ID, MPCC, inst),\ SRII 39 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SRII(MPCC_BG_G_Y, MPCC, inst),\ SRII 40 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SRII(MPCC_BG_R_CR, MPCC, inst),\ SRII 41 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SRII(MPCC_BG_B_CB, MPCC, inst),\ SRII 42 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SRII(MPCC_BG_B_CB, MPCC, inst),\ SRII 43 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SRII(MPCC_SM_CONTROL, MPCC, inst) SRII 46 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SRII(MUX, MPC_OUT, inst) SRII 35 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_TOP_GAIN, MPCC, inst),\ SRII 36 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),\ SRII 37 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_BOT_GAIN_OUTSIDE, MPCC, inst),\ SRII 38 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM, inst),\ SRII 39 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMA_START_CNTL_G, MPCC_OGAM, inst),\ SRII 40 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMA_START_CNTL_R, MPCC_OGAM, inst),\ SRII 41 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_B, MPCC_OGAM, inst),\ SRII 42 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_G, MPCC_OGAM, inst),\ SRII 43 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_R, MPCC_OGAM, inst),\ SRII 44 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM, inst),\ SRII 45 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM, inst),\ SRII 46 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMA_END_CNTL1_G, MPCC_OGAM, inst),\ SRII 47 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMA_END_CNTL2_G, MPCC_OGAM, inst),\ SRII 48 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMA_END_CNTL1_R, MPCC_OGAM, inst),\ SRII 49 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMA_END_CNTL2_R, MPCC_OGAM, inst),\ SRII 50 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM, inst),\ SRII 51 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMA_REGION_32_33, MPCC_OGAM, inst),\ SRII 52 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM, inst),\ SRII 53 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMB_START_CNTL_G, MPCC_OGAM, inst),\ SRII 54 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMB_START_CNTL_R, MPCC_OGAM, inst),\ SRII 55 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMB_SLOPE_CNTL_B, MPCC_OGAM, inst),\ SRII 56 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMB_SLOPE_CNTL_G, MPCC_OGAM, inst),\ SRII 57 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMB_SLOPE_CNTL_R, MPCC_OGAM, inst),\ SRII 58 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMB_END_CNTL1_B, MPCC_OGAM, inst),\ SRII 59 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM, inst),\ SRII 60 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMB_END_CNTL1_G, MPCC_OGAM, inst),\ SRII 61 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMB_END_CNTL2_G, MPCC_OGAM, inst),\ SRII 62 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMB_END_CNTL1_R, MPCC_OGAM, inst),\ SRII 63 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMB_END_CNTL2_R, MPCC_OGAM, inst),\ SRII 64 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM, inst),\ SRII 65 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_RAMB_REGION_32_33, MPCC_OGAM, inst),\ SRII 66 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_MEM_PWR_CTRL, MPCC, inst),\ SRII 67 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_LUT_INDEX, MPCC_OGAM, inst),\ SRII 68 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM, inst),\ SRII 69 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_LUT_DATA, MPCC_OGAM, inst),\ SRII 70 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(MPCC_OGAM_MODE, MPCC_OGAM, inst) SRII 74 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(CSC_MODE, MPC_OUT, inst),\ SRII 75 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(CSC_C11_C12_A, MPC_OUT, inst),\ SRII 76 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(CSC_C33_C34_A, MPC_OUT, inst),\ SRII 77 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(CSC_C11_C12_B, MPC_OUT, inst),\ SRII 78 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(CSC_C33_C34_B, MPC_OUT, inst),\ SRII 79 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(DENORM_CONTROL, MPC_OUT, inst),\ SRII 80 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(DENORM_CLAMP_G_Y, MPC_OUT, inst),\ SRII 81 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SRII(DENORM_CLAMP_B_CB, MPC_OUT, inst)