SRI                58 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h 	SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
SRI                59 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h 	SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
SRI                60 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h 	SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
SRI                61 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h 	SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
SRI                62 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h 	SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
SRI                63 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h 	SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
SRI                64 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h 	SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
SRI                65 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h 	SRI(BL1_PWM_USER_LEVEL, ABM, id), \
SRI                66 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h 	SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
SRI                67 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h 	SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
SRI                31 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h 	SRI(AZALIA_F0_CODEC_ENDPOINT_INDEX, AZF0ENDPOINT, id),\
SRI                32 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h 	SRI(AZALIA_F0_CODEC_ENDPOINT_DATA, AZF0ENDPOINT, id),\
SRI                34 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h 	SRI(AUX_CONTROL, DP_AUX, id), \
SRI                35 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h 	SRI(AUX_ARB_CONTROL, DP_AUX, id), \
SRI                36 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h 	SRI(AUX_SW_DATA, DP_AUX, id), \
SRI                37 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h 	SRI(AUX_SW_CONTROL, DP_AUX, id), \
SRI                38 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h 	SRI(AUX_INTERRUPT_CONTROL, DP_AUX, id), \
SRI                39 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h 	SRI(AUX_SW_STATUS, DP_AUX, id)
SRI                43 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h 	SRI(AUX_CONTROL, DP_AUX, id), \
SRI                44 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h 	SRI(AUX_ARB_CONTROL, DP_AUX, id), \
SRI                45 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h 	SRI(AUX_SW_DATA, DP_AUX, id), \
SRI                46 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h 	SRI(AUX_SW_CONTROL, DP_AUX, id), \
SRI                47 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h 	SRI(AUX_INTERRUPT_CONTROL, DP_AUX, id), \
SRI                48 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h 	SRI(AUX_SW_STATUS, DP_AUX, id), \
SRI                34 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRI(RESYNC_CNTL, PIXCLK, id), \
SRI                35 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRI(PLL_CNTL, BPHYC_PLL, id)
SRI                38 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRI(RESYNC_CNTL, PIXCLK, id), \
SRI                39 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRI(PLL_CNTL, DCCG_PLL, id)
SRI                42 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRI(PIXCLK_RESYNC_CNTL, PHYPLL, id)
SRI                60 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
SRI                83 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
SRI               109 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
SRI                85 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h 	SRI(SETUP, DC_I2C_DDC, id),\
SRI                86 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h 	SRI(SPEED, DC_I2C_DDC, id),\
SRI                87 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h 	SRI(HW_STATUS, DC_I2C_DDC, id),\
SRI                35 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h 	SRI(CUR_UPDATE, DCP, id), \
SRI                36 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h 	SRI(CUR_CONTROL, DCP, id), \
SRI                37 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h 	SRI(CUR_POSITION, DCP, id), \
SRI                38 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h 	SRI(CUR_HOT_SPOT, DCP, id), \
SRI                39 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h 	SRI(CUR_COLOR1, DCP, id), \
SRI                40 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h 	SRI(CUR_COLOR2, DCP, id), \
SRI                41 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h 	SRI(CUR_SIZE, DCP, id), \
SRI                42 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h 	SRI(CUR_SURFACE_ADDRESS_HIGH, DCP, id), \
SRI                43 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h 	SRI(CUR_SURFACE_ADDRESS, DCP, id), \
SRI                44 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h 	SRI(PRESCALE_GRPH_CONTROL, DCP, id), \
SRI                45 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h 	SRI(PRESCALE_VALUES_GRPH_R, DCP, id), \
SRI                46 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h 	SRI(PRESCALE_VALUES_GRPH_G, DCP, id), \
SRI                47 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h 	SRI(PRESCALE_VALUES_GRPH_B, DCP, id), \
SRI                48 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h 	SRI(INPUT_GAMMA_CONTROL, DCP, id), \
SRI                49 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h 	SRI(DC_LUT_WRITE_EN_MASK, DCP, id), \
SRI                50 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h 	SRI(DC_LUT_RW_MODE, DCP, id), \
SRI                51 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h 	SRI(DC_LUT_CONTROL, DCP, id), \
SRI                52 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h 	SRI(DC_LUT_RW_INDEX, DCP, id), \
SRI                53 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h 	SRI(DC_LUT_SEQ_COLOR, DCP, id), \
SRI                54 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h 	SRI(DEGAMMA_CONTROL, DCP, id)
SRI                58 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h 	SRI(DCFE_MEM_PWR_CTRL, CRTC, id)
SRI                62 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h 	SRI(DCFE_MEM_PWR_CTRL, DCFE, id)
SRI                40 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(AUX_CONTROL, DP_AUX, id), \
SRI                41 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id)
SRI                44 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DC_HPD_CONTROL, HPD, id)
SRI                51 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DIG_BE_CNTL, DIG, id), \
SRI                52 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DIG_BE_EN_CNTL, DIG, id), \
SRI                53 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_CONFIG, DP, id), \
SRI                54 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_DPHY_CNTL, DP, id), \
SRI                55 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_DPHY_PRBS_CNTL, DP, id), \
SRI                56 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
SRI                57 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_DPHY_SYM0, DP, id), \
SRI                58 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_DPHY_SYM1, DP, id), \
SRI                59 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_DPHY_SYM2, DP, id), \
SRI                60 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
SRI                61 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_LINK_CNTL, DP, id), \
SRI                62 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_LINK_FRAMING_CNTL, DP, id), \
SRI                63 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_MSE_SAT0, DP, id), \
SRI                64 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_MSE_SAT1, DP, id), \
SRI                65 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_MSE_SAT2, DP, id), \
SRI                66 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_MSE_SAT_UPDATE, DP, id), \
SRI                67 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_SEC_CNTL, DP, id), \
SRI                68 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_VID_STREAM_CNTL, DP, id), \
SRI                69 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_DPHY_FAST_TRAINING, DP, id), \
SRI                70 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_SEC_CNTL1, DP, id)
SRI                74 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
SRI                75 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
SRI                79 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
SRI                84 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
SRI                85 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
SRI                90 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
SRI                91 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
SRI                92 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \
SRI                97 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
SRI                98 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \
SRI               103 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
SRI               104 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
SRI               105 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id)
SRI                35 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SRI(GRPH_ENABLE, DCP, id),\
SRI                36 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SRI(GRPH_CONTROL, DCP, id),\
SRI                37 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SRI(GRPH_X_START, DCP, id),\
SRI                38 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SRI(GRPH_Y_START, DCP, id),\
SRI                39 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SRI(GRPH_X_END, DCP, id),\
SRI                40 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SRI(GRPH_Y_END, DCP, id),\
SRI                41 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SRI(GRPH_PITCH, DCP, id),\
SRI                42 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SRI(HW_ROTATION, DCP, id),\
SRI                43 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SRI(GRPH_SWAP_CNTL, DCP, id),\
SRI                44 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SRI(PRESCALE_GRPH_CONTROL, DCP, id),\
SRI                45 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SRI(GRPH_UPDATE, DCP, id),\
SRI                46 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SRI(GRPH_FLIP_CONTROL, DCP, id),\
SRI                47 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SRI(GRPH_PRIMARY_SURFACE_ADDRESS, DCP, id),\
SRI                48 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SRI(GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, DCP, id),\
SRI                49 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SRI(GRPH_SECONDARY_SURFACE_ADDRESS, DCP, id),\
SRI                50 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SRI(GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, DCP, id),\
SRI                51 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SRI(DPG_PIPE_ARBITRATION_CONTROL1, DMIF_PG, id),\
SRI                52 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SRI(DPG_WATERMARK_MASK_CONTROL, DMIF_PG, id),\
SRI                53 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SRI(DPG_PIPE_URGENCY_CONTROL, DMIF_PG, id),\
SRI                54 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SRI(DPG_PIPE_STUTTER_CONTROL, DMIF_PG, id),\
SRI                55 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SRI(DMIF_BUFFER_CONTROL, PIPE, id)
SRI                58 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SRI(DVMM_PTE_CONTROL, DCP, id),\
SRI                59 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SRI(DVMM_PTE_ARB_CONTROL, DCP, id)
SRI                63 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SRI(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, DMIF_PG, id)
SRI                67 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SRI(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, DCP, id)
SRI                76 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SRI(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, DCP, id),\
SRI                77 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SRI(DPG_PIPE_STUTTER_CONTROL2, DMIF_PG, id),\
SRI                78 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SRI(DPG_PIPE_LOW_POWER_CONTROL, DMIF_PG, id),\
SRI                44 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \
SRI                45 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \
SRI                46 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	SRI(FMT_CONTROL, FMT, id), \
SRI                47 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	SRI(FMT_DITHER_RAND_R_SEED, FMT, id), \
SRI                48 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	SRI(FMT_DITHER_RAND_G_SEED, FMT, id), \
SRI                49 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	SRI(FMT_DITHER_RAND_B_SEED, FMT, id), \
SRI                50 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	SRI(FMT_CLAMP_CNTL, FMT, id), \
SRI                51 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	SRI(FMT_CLAMP_COMPONENT_R, FMT, id), \
SRI                52 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	SRI(FMT_CLAMP_COMPONENT_G, FMT, id), \
SRI                53 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	SRI(FMT_CLAMP_COMPONENT_B, FMT, id)
SRI                57 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \
SRI                58 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \
SRI                59 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id)
SRI                63 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \
SRI                64 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \
SRI                65 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id)
SRI                69 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \
SRI                70 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \
SRI                71 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id)
SRI                75 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \
SRI                76 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \
SRI                77 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id), \
SRI                78 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	SRI(CONTROL, FMT_MEMORY, id)
SRI                82 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h 	SRI(CONTROL, FMT_MEMORY, id)
SRI                44 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(AFMT_AVI_INFO0, DIG, id), \
SRI                45 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(AFMT_AVI_INFO1, DIG, id), \
SRI                46 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(AFMT_AVI_INFO2, DIG, id), \
SRI                47 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(AFMT_AVI_INFO3, DIG, id)
SRI                50 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(AFMT_GENERIC_0, DIG, id), \
SRI                51 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(AFMT_GENERIC_1, DIG, id), \
SRI                52 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(AFMT_GENERIC_2, DIG, id), \
SRI                53 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(AFMT_GENERIC_3, DIG, id), \
SRI                54 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(AFMT_GENERIC_4, DIG, id), \
SRI                55 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(AFMT_GENERIC_5, DIG, id), \
SRI                56 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(AFMT_GENERIC_6, DIG, id), \
SRI                57 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(AFMT_GENERIC_7, DIG, id), \
SRI                58 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(AFMT_GENERIC_HDR, DIG, id), \
SRI                59 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(AFMT_INFOFRAME_CONTROL0, DIG, id), \
SRI                60 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(AFMT_VBI_PACKET_CONTROL, DIG, id), \
SRI                61 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(AFMT_AUDIO_PACKET_CONTROL, DIG, id), \
SRI                62 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(AFMT_AUDIO_PACKET_CONTROL2, DIG, id), \
SRI                63 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(AFMT_AUDIO_SRC_CONTROL, DIG, id), \
SRI                64 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(AFMT_60958_0, DIG, id), \
SRI                65 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(AFMT_60958_1, DIG, id), \
SRI                66 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(AFMT_60958_2, DIG, id), \
SRI                67 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(DIG_FE_CNTL, DIG, id), \
SRI                68 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(HDMI_CONTROL, DIG, id), \
SRI                69 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(HDMI_GC, DIG, id), \
SRI                70 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \
SRI                71 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \
SRI                72 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \
SRI                73 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \
SRI                74 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \
SRI                75 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\
SRI                76 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
SRI                77 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(HDMI_ACR_32_0, DIG, id),\
SRI                78 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(HDMI_ACR_32_1, DIG, id),\
SRI                79 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(HDMI_ACR_44_0, DIG, id),\
SRI                80 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(HDMI_ACR_44_1, DIG, id),\
SRI                81 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(HDMI_ACR_48_0, DIG, id),\
SRI                82 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(HDMI_ACR_48_1, DIG, id),\
SRI                83 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(TMDS_CNTL, DIG, id), \
SRI                84 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(DP_MSE_RATE_CNTL, DP, id), \
SRI                85 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(DP_MSE_RATE_UPDATE, DP, id), \
SRI                86 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(DP_PIXEL_FORMAT, DP, id), \
SRI                87 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(DP_SEC_CNTL, DP, id), \
SRI                88 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(DP_STEER_FIFO, DP, id), \
SRI                89 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(DP_VID_M, DP, id), \
SRI                90 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(DP_VID_N, DP, id), \
SRI                91 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(DP_VID_STREAM_CNTL, DP, id), \
SRI                92 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(DP_VID_TIMING, DP, id), \
SRI                93 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(DP_SEC_AUD_N, DP, id), \
SRI                94 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(DP_SEC_TIMESTAMP, DP, id)
SRI                98 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(AFMT_CNTL, DIG, id)
SRI               102 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(AFMT_CNTL, DIG, id),\
SRI               103 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(AFMT_VBI_PACKET_CONTROL1, DIG, id),\
SRI               104 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \
SRI               105 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \
SRI               106 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(DP_DB_CNTL, DP, id), \
SRI               107 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(DP_MSA_MISC, DP, id), \
SRI               108 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(DP_MSA_COLORIMETRY, DP, id), \
SRI               109 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(DP_MSA_TIMING_PARAM1, DP, id), \
SRI               110 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(DP_MSA_TIMING_PARAM2, DP, id), \
SRI               111 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(DP_MSA_TIMING_PARAM3, DP, id), \
SRI               112 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(DP_MSA_TIMING_PARAM4, DP, id), \
SRI               113 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(HDMI_DB_CONTROL, DIG, id)
SRI                39 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(LB_DATA_FORMAT, LB, id), \
SRI                40 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(GAMUT_REMAP_CONTROL, DCP, id), \
SRI                41 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(GAMUT_REMAP_C11_C12, DCP, id), \
SRI                42 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(GAMUT_REMAP_C13_C14, DCP, id), \
SRI                43 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(GAMUT_REMAP_C21_C22, DCP, id), \
SRI                44 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(GAMUT_REMAP_C23_C24, DCP, id), \
SRI                45 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(GAMUT_REMAP_C31_C32, DCP, id), \
SRI                46 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(GAMUT_REMAP_C33_C34, DCP, id), \
SRI                47 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(OUTPUT_CSC_C11_C12, DCP, id), \
SRI                48 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(OUTPUT_CSC_C13_C14, DCP, id), \
SRI                49 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(OUTPUT_CSC_C21_C22, DCP, id), \
SRI                50 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(OUTPUT_CSC_C23_C24, DCP, id), \
SRI                51 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(OUTPUT_CSC_C31_C32, DCP, id), \
SRI                52 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(OUTPUT_CSC_C33_C34, DCP, id), \
SRI                53 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(OUTPUT_CSC_CONTROL, DCP, id), \
SRI                54 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(REGAMMA_CNTLA_START_CNTL, DCP, id), \
SRI                55 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(REGAMMA_CNTLA_SLOPE_CNTL, DCP, id), \
SRI                56 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(REGAMMA_CNTLA_END_CNTL1, DCP, id), \
SRI                57 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(REGAMMA_CNTLA_END_CNTL2, DCP, id), \
SRI                58 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(REGAMMA_CNTLA_REGION_0_1, DCP, id), \
SRI                59 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(REGAMMA_CNTLA_REGION_2_3, DCP, id), \
SRI                60 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(REGAMMA_CNTLA_REGION_4_5, DCP, id), \
SRI                61 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(REGAMMA_CNTLA_REGION_6_7, DCP, id), \
SRI                62 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(REGAMMA_CNTLA_REGION_8_9, DCP, id), \
SRI                63 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(REGAMMA_CNTLA_REGION_10_11, DCP, id), \
SRI                64 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(REGAMMA_CNTLA_REGION_12_13, DCP, id), \
SRI                65 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(REGAMMA_CNTLA_REGION_14_15, DCP, id), \
SRI                66 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(REGAMMA_LUT_WRITE_EN_MASK, DCP, id), \
SRI                67 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(REGAMMA_LUT_INDEX, DCP, id), \
SRI                68 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(REGAMMA_LUT_DATA, DCP, id), \
SRI                69 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(REGAMMA_CONTROL, DCP, id), \
SRI                70 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(DENORM_CONTROL, DCP, id), \
SRI                71 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(DCP_SPATIAL_DITHER_CNTL, DCP, id), \
SRI                72 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(OUT_ROUND_CONTROL, DCP, id), \
SRI                73 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(OUT_CLAMP_CONTROL_R_CR, DCP, id), \
SRI                74 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(OUT_CLAMP_CONTROL_G_Y, DCP, id), \
SRI                75 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(OUT_CLAMP_CONTROL_B_CB, DCP, id), \
SRI                76 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(SCL_MODE, SCL, id), \
SRI                77 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(SCL_TAP_CONTROL, SCL, id), \
SRI                78 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(SCL_CONTROL, SCL, id), \
SRI                79 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(SCL_BYPASS_CONTROL, SCL, id), \
SRI                80 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(EXT_OVERSCAN_LEFT_RIGHT, SCL, id), \
SRI                81 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(EXT_OVERSCAN_TOP_BOTTOM, SCL, id), \
SRI                82 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(SCL_VERT_FILTER_CONTROL, SCL, id), \
SRI                83 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(SCL_HORZ_FILTER_CONTROL, SCL, id), \
SRI                84 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(SCL_COEF_RAM_SELECT, SCL, id), \
SRI                85 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(SCL_COEF_RAM_TAP_DATA, SCL, id), \
SRI                86 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(VIEWPORT_START, SCL, id), \
SRI                87 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(VIEWPORT_SIZE, SCL, id), \
SRI                88 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(SCL_HORZ_FILTER_SCALE_RATIO, SCL, id), \
SRI                89 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(SCL_VERT_FILTER_SCALE_RATIO, SCL, id), \
SRI                90 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(SCL_HORZ_FILTER_INIT, SCL, id), \
SRI                91 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(SCL_VERT_FILTER_INIT, SCL, id), \
SRI                92 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(SCL_AUTOMATIC_MODE_CONTROL, SCL, id), \
SRI                93 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(LB_MEMORY_CTRL, LB, id), \
SRI                94 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(SCL_UPDATE, SCL, id), \
SRI                95 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(SCL_F_SHARP_CONTROL, SCL, id)
SRI                99 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id)
SRI               103 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(DCFE_MEM_PWR_CTRL, CRTC, id), \
SRI               104 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(DCFE_MEM_PWR_STATUS, CRTC, id)
SRI               108 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \
SRI               109 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(DCFE_MEM_PWR_STATUS, DCFE, id)
SRI               259 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
SRI                45 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_GAMUT_REMAP_CONTROL, CM, id),\
SRI                46 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_GAMUT_REMAP_C11_C12, CM, id),\
SRI                47 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_GAMUT_REMAP_C13_C14, CM, id),\
SRI                48 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_GAMUT_REMAP_C21_C22, CM, id),\
SRI                49 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_GAMUT_REMAP_C23_C24, CM, id),\
SRI                50 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_GAMUT_REMAP_C31_C32, CM, id),\
SRI                51 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_GAMUT_REMAP_C33_C34, CM, id),\
SRI                52 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \
SRI                53 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \
SRI                54 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(OTG_H_BLANK, DSCL, id), \
SRI                55 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(OTG_V_BLANK, DSCL, id), \
SRI                56 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(SCL_MODE, DSCL, id), \
SRI                57 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(LB_DATA_FORMAT, DSCL, id), \
SRI                58 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(LB_MEMORY_CTRL, DSCL, id), \
SRI                59 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(DSCL_AUTOCAL, DSCL, id), \
SRI                60 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(SCL_BLACK_OFFSET, DSCL, id), \
SRI                61 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(SCL_TAP_CONTROL, DSCL, id), \
SRI                62 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \
SRI                63 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(SCL_COEF_RAM_TAP_DATA, DSCL, id), \
SRI                64 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(DSCL_2TAP_CONTROL, DSCL, id), \
SRI                65 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(MPC_SIZE, DSCL, id), \
SRI                66 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id), \
SRI                67 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id), \
SRI                68 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(SCL_HORZ_FILTER_SCALE_RATIO_C, DSCL, id), \
SRI                69 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(SCL_VERT_FILTER_SCALE_RATIO_C, DSCL, id), \
SRI                70 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(SCL_HORZ_FILTER_INIT, DSCL, id), \
SRI                71 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(SCL_HORZ_FILTER_INIT_C, DSCL, id), \
SRI                72 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(SCL_VERT_FILTER_INIT, DSCL, id), \
SRI                73 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(SCL_VERT_FILTER_INIT_BOT, DSCL, id), \
SRI                74 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(SCL_VERT_FILTER_INIT_C, DSCL, id), \
SRI                75 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(SCL_VERT_FILTER_INIT_BOT_C, DSCL, id), \
SRI                76 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(RECOUT_START, DSCL, id), \
SRI                77 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(RECOUT_SIZE, DSCL, id), \
SRI                78 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_ICSC_CONTROL, CM, id), \
SRI                79 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_ICSC_C11_C12, CM, id), \
SRI                80 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_ICSC_C33_C34, CM, id), \
SRI                81 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_DGAM_RAMB_START_CNTL_B, CM, id), \
SRI                82 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_DGAM_RAMB_START_CNTL_G, CM, id), \
SRI                83 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_DGAM_RAMB_START_CNTL_R, CM, id), \
SRI                84 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_DGAM_RAMB_SLOPE_CNTL_B, CM, id), \
SRI                85 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_DGAM_RAMB_SLOPE_CNTL_G, CM, id), \
SRI                86 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_DGAM_RAMB_SLOPE_CNTL_R, CM, id), \
SRI                87 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_DGAM_RAMB_END_CNTL1_B, CM, id), \
SRI                88 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_DGAM_RAMB_END_CNTL2_B, CM, id), \
SRI                89 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_DGAM_RAMB_END_CNTL1_G, CM, id), \
SRI                90 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_DGAM_RAMB_END_CNTL2_G, CM, id), \
SRI                91 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_DGAM_RAMB_END_CNTL1_R, CM, id), \
SRI                92 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_DGAM_RAMB_END_CNTL2_R, CM, id), \
SRI                93 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_DGAM_RAMB_REGION_0_1, CM, id), \
SRI                94 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_DGAM_RAMB_REGION_14_15, CM, id), \
SRI                95 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_DGAM_RAMA_START_CNTL_B, CM, id), \
SRI                96 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_DGAM_RAMA_START_CNTL_G, CM, id), \
SRI                97 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_DGAM_RAMA_START_CNTL_R, CM, id), \
SRI                98 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_DGAM_RAMA_SLOPE_CNTL_B, CM, id), \
SRI                99 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_DGAM_RAMA_SLOPE_CNTL_G, CM, id), \
SRI               100 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_DGAM_RAMA_SLOPE_CNTL_R, CM, id), \
SRI               101 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_DGAM_RAMA_END_CNTL1_B, CM, id), \
SRI               102 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_DGAM_RAMA_END_CNTL2_B, CM, id), \
SRI               103 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_DGAM_RAMA_END_CNTL1_G, CM, id), \
SRI               104 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_DGAM_RAMA_END_CNTL2_G, CM, id), \
SRI               105 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_DGAM_RAMA_END_CNTL1_R, CM, id), \
SRI               106 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_DGAM_RAMA_END_CNTL2_R, CM, id), \
SRI               107 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_DGAM_RAMA_REGION_0_1, CM, id), \
SRI               108 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_DGAM_RAMA_REGION_14_15, CM, id), \
SRI               109 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_MEM_PWR_CTRL, CM, id), \
SRI               110 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_DGAM_LUT_WRITE_EN_MASK, CM, id), \
SRI               111 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_DGAM_LUT_INDEX, CM, id), \
SRI               112 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_DGAM_LUT_DATA, CM, id), \
SRI               113 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_CONTROL, CM, id), \
SRI               114 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_DGAM_CONTROL, CM, id), \
SRI               115 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_TEST_DEBUG_INDEX, CM, id), \
SRI               116 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_TEST_DEBUG_DATA, CM, id), \
SRI               117 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(FORMAT_CONTROL, CNVC_CFG, id), \
SRI               118 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
SRI               119 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
SRI               120 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CURSOR0_COLOR0, CNVC_CUR, id), \
SRI               121 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CURSOR0_COLOR1, CNVC_CUR, id), \
SRI               122 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CURSOR0_FP_SCALE_BIAS, CNVC_CUR, id), \
SRI               123 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(DPP_CONTROL, DPP_TOP, id), \
SRI               124 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_HDR_MULT_COEF, CM, id)
SRI               130 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_COMA_C11_C12, CM, id),\
SRI               131 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_COMA_C33_C34, CM, id),\
SRI               132 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_COMB_C11_C12, CM, id),\
SRI               133 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_COMB_C33_C34, CM, id),\
SRI               134 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_OCSC_CONTROL, CM, id), \
SRI               135 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_OCSC_C11_C12, CM, id), \
SRI               136 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_OCSC_C33_C34, CM, id), \
SRI               137 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_BNS_VALUES_R, CM, id), \
SRI               138 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_BNS_VALUES_G, CM, id), \
SRI               139 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_BNS_VALUES_B, CM, id), \
SRI               140 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_MEM_PWR_CTRL, CM, id), \
SRI               141 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_RGAM_LUT_DATA, CM, id), \
SRI               142 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_RGAM_LUT_WRITE_EN_MASK, CM, id),\
SRI               143 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_RGAM_LUT_INDEX, CM, id), \
SRI               144 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_RGAM_RAMB_START_CNTL_B, CM, id), \
SRI               145 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_RGAM_RAMB_START_CNTL_G, CM, id), \
SRI               146 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_RGAM_RAMB_START_CNTL_R, CM, id), \
SRI               147 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_RGAM_RAMB_SLOPE_CNTL_B, CM, id), \
SRI               148 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_RGAM_RAMB_SLOPE_CNTL_G, CM, id), \
SRI               149 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_RGAM_RAMB_SLOPE_CNTL_R, CM, id), \
SRI               150 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_RGAM_RAMB_END_CNTL1_B, CM, id), \
SRI               151 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_RGAM_RAMB_END_CNTL2_B, CM, id), \
SRI               152 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_RGAM_RAMB_END_CNTL1_G, CM, id), \
SRI               153 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_RGAM_RAMB_END_CNTL2_G, CM, id), \
SRI               154 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_RGAM_RAMB_END_CNTL1_R, CM, id), \
SRI               155 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_RGAM_RAMB_END_CNTL2_R, CM, id), \
SRI               156 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_RGAM_RAMB_REGION_0_1, CM, id), \
SRI               157 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_RGAM_RAMB_REGION_32_33, CM, id), \
SRI               158 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_RGAM_RAMA_START_CNTL_B, CM, id), \
SRI               159 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_RGAM_RAMA_START_CNTL_G, CM, id), \
SRI               160 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_RGAM_RAMA_START_CNTL_R, CM, id), \
SRI               161 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_RGAM_RAMA_SLOPE_CNTL_B, CM, id), \
SRI               162 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_RGAM_RAMA_SLOPE_CNTL_G, CM, id), \
SRI               163 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_RGAM_RAMA_SLOPE_CNTL_R, CM, id), \
SRI               164 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_RGAM_RAMA_END_CNTL1_B, CM, id), \
SRI               165 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_RGAM_RAMA_END_CNTL2_B, CM, id), \
SRI               166 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_RGAM_RAMA_END_CNTL1_G, CM, id), \
SRI               167 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_RGAM_RAMA_END_CNTL2_G, CM, id), \
SRI               168 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_RGAM_RAMA_END_CNTL1_R, CM, id), \
SRI               169 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_RGAM_RAMA_END_CNTL2_R, CM, id), \
SRI               170 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_RGAM_RAMA_REGION_0_1, CM, id), \
SRI               171 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_RGAM_RAMA_REGION_32_33, CM, id), \
SRI               172 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_RGAM_CONTROL, CM, id), \
SRI               173 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_IGAM_CONTROL, CM, id), \
SRI               174 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_IGAM_LUT_RW_CONTROL, CM, id), \
SRI               175 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_IGAM_LUT_RW_INDEX, CM, id), \
SRI               176 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_IGAM_LUT_SEQ_COLOR, CM, id), \
SRI               177 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CURSOR_CONTROL, CURSOR, id), \
SRI               178 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_CMOUT_CONTROL, CM, id)
SRI                54 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(WB_ENABLE, CNV, inst),\
SRI                55 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(WB_EC_CONFIG, CNV, inst),\
SRI                56 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(CNV_MODE, CNV, inst),\
SRI                57 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(WB_SOFT_RESET, CNV, inst),\
SRI                58 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
SRI                59 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
SRI                60 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\
SRI                61 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\
SRI                62 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\
SRI                63 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB, inst),\
SRI                64 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\
SRI                65 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB, inst),\
SRI                66 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\
SRI                67 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB, inst),\
SRI                68 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\
SRI                69 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB, inst),\
SRI                70 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\
SRI                71 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB, inst),\
SRI                72 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\
SRI                73 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB, inst),\
SRI                74 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\
SRI                75 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB, inst),\
SRI                76 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\
SRI                77 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB, inst),\
SRI                78 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\
SRI                79 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MCIF_WB, inst),\
SRI                80 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\
SRI                81 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_WATERMARK, MCIF_WB, inst),\
SRI                82 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_WARM_UP_CNTL, MCIF_WB, inst),\
SRI                83 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\
SRI                84 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst)
SRI                35 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCHUBP_CNTL, HUBP, id),\
SRI                36 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(HUBPREQ_DEBUG_DB, HUBP, id),\
SRI                37 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(HUBPREQ_DEBUG, HUBP, id),\
SRI                38 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCSURF_ADDR_CONFIG, HUBP, id),\
SRI                39 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCSURF_TILING_CONFIG, HUBP, id),\
SRI                40 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCSURF_SURFACE_PITCH, HUBPREQ, id),\
SRI                41 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCSURF_SURFACE_PITCH_C, HUBPREQ, id),\
SRI                42 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCSURF_SURFACE_CONFIG, HUBP, id),\
SRI                43 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCSURF_FLIP_CONTROL, HUBPREQ, id),\
SRI                44 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCSURF_PRI_VIEWPORT_DIMENSION, HUBP, id), \
SRI                45 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCSURF_PRI_VIEWPORT_START, HUBP, id), \
SRI                46 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCSURF_SEC_VIEWPORT_DIMENSION, HUBP, id), \
SRI                47 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCSURF_SEC_VIEWPORT_START, HUBP, id), \
SRI                48 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCSURF_PRI_VIEWPORT_DIMENSION_C, HUBP, id), \
SRI                49 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCSURF_PRI_VIEWPORT_START_C, HUBP, id), \
SRI                50 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
SRI                51 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCSURF_PRIMARY_SURFACE_ADDRESS, HUBPREQ, id),\
SRI                52 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
SRI                53 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCSURF_SECONDARY_SURFACE_ADDRESS, HUBPREQ, id),\
SRI                54 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
SRI                55 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS, HUBPREQ, id),\
SRI                56 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
SRI                57 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS, HUBPREQ, id),\
SRI                58 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
SRI                59 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_C, HUBPREQ, id),\
SRI                60 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
SRI                61 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, HUBPREQ, id),\
SRI                62 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCSURF_SURFACE_INUSE, HUBPREQ, id),\
SRI                63 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCSURF_SURFACE_INUSE_HIGH, HUBPREQ, id),\
SRI                64 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCSURF_SURFACE_INUSE_C, HUBPREQ, id),\
SRI                65 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCSURF_SURFACE_INUSE_HIGH_C, HUBPREQ, id),\
SRI                66 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCSURF_SURFACE_EARLIEST_INUSE, HUBPREQ, id),\
SRI                67 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, HUBPREQ, id),\
SRI                68 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCSURF_SURFACE_EARLIEST_INUSE_C, HUBPREQ, id),\
SRI                69 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, HUBPREQ, id),\
SRI                70 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCSURF_SURFACE_CONTROL, HUBPREQ, id),\
SRI                71 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(HUBPRET_CONTROL, HUBPRET, id),\
SRI                72 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCN_EXPANSION_MODE, HUBPREQ, id),\
SRI                73 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCHUBP_REQ_SIZE_CONFIG, HUBP, id),\
SRI                74 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCHUBP_REQ_SIZE_CONFIG_C, HUBP, id),\
SRI                75 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(BLANK_OFFSET_0, HUBPREQ, id),\
SRI                76 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(BLANK_OFFSET_1, HUBPREQ, id),\
SRI                77 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DST_DIMENSIONS, HUBPREQ, id),\
SRI                78 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DST_AFTER_SCALER, HUBPREQ, id),\
SRI                79 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(VBLANK_PARAMETERS_0, HUBPREQ, id),\
SRI                80 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(REF_FREQ_TO_PIX_FREQ, HUBPREQ, id),\
SRI                81 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(VBLANK_PARAMETERS_1, HUBPREQ, id),\
SRI                82 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(VBLANK_PARAMETERS_3, HUBPREQ, id),\
SRI                83 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(NOM_PARAMETERS_4, HUBPREQ, id),\
SRI                84 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(NOM_PARAMETERS_5, HUBPREQ, id),\
SRI                85 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(PER_LINE_DELIVERY_PRE, HUBPREQ, id),\
SRI                86 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(PER_LINE_DELIVERY, HUBPREQ, id),\
SRI                87 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(VBLANK_PARAMETERS_2, HUBPREQ, id),\
SRI                88 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(VBLANK_PARAMETERS_4, HUBPREQ, id),\
SRI                89 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(NOM_PARAMETERS_6, HUBPREQ, id),\
SRI                90 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(NOM_PARAMETERS_7, HUBPREQ, id),\
SRI                91 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCN_TTU_QOS_WM, HUBPREQ, id),\
SRI                92 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCN_GLOBAL_TTU_CNTL, HUBPREQ, id),\
SRI                93 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCN_SURF0_TTU_CNTL0, HUBPREQ, id),\
SRI                94 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCN_SURF0_TTU_CNTL1, HUBPREQ, id),\
SRI                95 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCN_SURF1_TTU_CNTL0, HUBPREQ, id),\
SRI                96 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\
SRI                97 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCN_CUR0_TTU_CNTL0, HUBPREQ, id),\
SRI                98 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCN_CUR0_TTU_CNTL1, HUBPREQ, id),\
SRI                99 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(HUBP_CLK_CNTL, HUBP, id)
SRI               103 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(NOM_PARAMETERS_0, HUBPREQ, id),\
SRI               104 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(NOM_PARAMETERS_1, HUBPREQ, id),\
SRI               105 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(NOM_PARAMETERS_2, HUBPREQ, id),\
SRI               106 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(NOM_PARAMETERS_3, HUBPREQ, id),\
SRI               107 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id)
SRI               112 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(PREFETCH_SETTINS, HUBPREQ, id),\
SRI               113 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(PREFETCH_SETTINS_C, HUBPREQ, id),\
SRI               114 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, HUBPREQ, id),\
SRI               115 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, HUBPREQ, id),\
SRI               116 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, HUBPREQ, id),\
SRI               117 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, HUBPREQ, id),\
SRI               118 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, HUBPREQ, id),\
SRI               119 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, HUBPREQ, id),\
SRI               120 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, HUBPREQ, id),\
SRI               121 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, HUBPREQ, id),\
SRI               122 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, HUBPREQ, id),\
SRI               123 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, HUBPREQ, id),\
SRI               124 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, HUBPREQ, id),\
SRI               125 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, HUBPREQ, id),\
SRI               126 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, HUBPREQ, id),\
SRI               127 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, HUBPREQ, id),\
SRI               128 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(CURSOR_SETTINS, HUBPREQ, id), \
SRI               129 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR, id), \
SRI               130 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(CURSOR_SURFACE_ADDRESS, CURSOR, id), \
SRI               131 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(CURSOR_SIZE, CURSOR, id), \
SRI               132 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(CURSOR_CONTROL, CURSOR, id), \
SRI               133 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(CURSOR_POSITION, CURSOR, id), \
SRI               134 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(CURSOR_HOT_SPOT, CURSOR, id), \
SRI               135 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	SRI(CURSOR_DST_OFFSET, CURSOR, id)
SRI                35 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h 	SRI(FORMAT_CONTROL, CNVC_CFG, id), \
SRI                36 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h 	SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
SRI                37 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h 	SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
SRI                38 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h 	SRI(CURSOR0_COLOR0, CNVC_CUR, id), \
SRI                39 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h 	SRI(CURSOR0_COLOR1, CNVC_CUR, id)
SRI                43 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h 	SRI(CURSOR_SETTINS, HUBPREQ, id), \
SRI                44 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h 	SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR, id), \
SRI                45 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h 	SRI(CURSOR_SURFACE_ADDRESS, CURSOR, id), \
SRI                46 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h 	SRI(CURSOR_SIZE, CURSOR, id), \
SRI                47 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h 	SRI(CURSOR_CONTROL, CURSOR, id), \
SRI                48 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h 	SRI(CURSOR_POSITION, CURSOR, id), \
SRI                49 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h 	SRI(CURSOR_HOT_SPOT, CURSOR, id), \
SRI                50 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h 	SRI(CURSOR_DST_OFFSET, CURSOR, id)
SRI                55 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h 	SRI(CURSOR_SETTINGS, HUBPREQ, id), \
SRI                56 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h 	SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id), \
SRI                57 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h 	SRI(CURSOR_SURFACE_ADDRESS, CURSOR0_, id), \
SRI                58 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h 	SRI(CURSOR_SIZE, CURSOR0_, id), \
SRI                59 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h 	SRI(CURSOR_CONTROL, CURSOR0_, id), \
SRI                60 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h 	SRI(CURSOR_POSITION, CURSOR0_, id), \
SRI                61 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h 	SRI(CURSOR_HOT_SPOT, CURSOR0_, id), \
SRI                62 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h 	SRI(CURSOR_DST_OFFSET, CURSOR0_, id)
SRI                36 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	SRI(AUX_CONTROL, DP_AUX, id), \
SRI                37 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id)
SRI                40 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	SRI(DC_HPD_CONTROL, HPD, id)
SRI                43 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	SRI(DIG_BE_CNTL, DIG, id), \
SRI                44 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	SRI(DIG_BE_EN_CNTL, DIG, id), \
SRI                45 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	SRI(TMDS_CTL_BITS, DIG, id), \
SRI                46 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	SRI(DP_CONFIG, DP, id), \
SRI                47 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	SRI(DP_DPHY_CNTL, DP, id), \
SRI                48 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	SRI(DP_DPHY_PRBS_CNTL, DP, id), \
SRI                49 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
SRI                50 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	SRI(DP_DPHY_SYM0, DP, id), \
SRI                51 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	SRI(DP_DPHY_SYM1, DP, id), \
SRI                52 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	SRI(DP_DPHY_SYM2, DP, id), \
SRI                53 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
SRI                54 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	SRI(DP_LINK_CNTL, DP, id), \
SRI                55 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	SRI(DP_LINK_FRAMING_CNTL, DP, id), \
SRI                56 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	SRI(DP_MSE_SAT0, DP, id), \
SRI                57 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	SRI(DP_MSE_SAT1, DP, id), \
SRI                58 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	SRI(DP_MSE_SAT2, DP, id), \
SRI                59 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	SRI(DP_MSE_SAT_UPDATE, DP, id), \
SRI                60 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	SRI(DP_SEC_CNTL, DP, id), \
SRI                61 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	SRI(DP_VID_STREAM_CNTL, DP, id), \
SRI                62 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	SRI(DP_DPHY_FAST_TRAINING, DP, id), \
SRI                63 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	SRI(DP_SEC_CNTL1, DP, id), \
SRI                64 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
SRI                65 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
SRI                66 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id)
SRI                37 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h 	SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \
SRI                38 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h 	SRI(FMT_CONTROL, FMT, id), \
SRI                39 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h 	SRI(FMT_DITHER_RAND_R_SEED, FMT, id), \
SRI                40 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h 	SRI(FMT_DITHER_RAND_G_SEED, FMT, id), \
SRI                41 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h 	SRI(FMT_DITHER_RAND_B_SEED, FMT, id), \
SRI                42 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h 	SRI(FMT_CLAMP_CNTL, FMT, id), \
SRI                43 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h 	SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \
SRI                44 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h 	SRI(FMT_MAP420_MEMORY_CONTROL, FMT, id), \
SRI                45 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h 	SRI(OPPBUF_CONTROL, OPPBUF, id),\
SRI                46 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h 	SRI(OPPBUF_3D_PARAMETERS_0, OPPBUF, id), \
SRI                47 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h 	SRI(OPPBUF_3D_PARAMETERS_1, OPPBUF, id), \
SRI                48 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h 	SRI(OPP_PIPE_CONTROL, OPP_PIPE, id)
SRI                35 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
SRI                36 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_VUPDATE_PARAM, OTG, inst),\
SRI                37 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_VREADY_PARAM, OTG, inst),\
SRI                38 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_BLANK_CONTROL, OTG, inst),\
SRI                39 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
SRI                40 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
SRI                41 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
SRI                42 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_H_TOTAL, OTG, inst),\
SRI                43 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_H_BLANK_START_END, OTG, inst),\
SRI                44 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_H_SYNC_A, OTG, inst),\
SRI                45 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\
SRI                46 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_H_TIMING_CNTL, OTG, inst),\
SRI                47 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_V_TOTAL, OTG, inst),\
SRI                48 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_V_BLANK_START_END, OTG, inst),\
SRI                49 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_V_SYNC_A, OTG, inst),\
SRI                50 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\
SRI                51 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_INTERLACE_CONTROL, OTG, inst),\
SRI                52 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_CONTROL, OTG, inst),\
SRI                53 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_STEREO_CONTROL, OTG, inst),\
SRI                54 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
SRI                55 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_STEREO_STATUS, OTG, inst),\
SRI                56 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_V_TOTAL_MAX, OTG, inst),\
SRI                57 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_V_TOTAL_MID, OTG, inst),\
SRI                58 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_V_TOTAL_MIN, OTG, inst),\
SRI                59 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
SRI                60 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_TRIGA_CNTL, OTG, inst),\
SRI                61 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\
SRI                62 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\
SRI                63 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\
SRI                64 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_STATUS, OTG, inst),\
SRI                65 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_STATUS_POSITION, OTG, inst),\
SRI                66 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_NOM_VERT_POSITION, OTG, inst),\
SRI                67 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_BLACK_COLOR, OTG, inst),\
SRI                68 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_CLOCK_CONTROL, OTG, inst),\
SRI                69 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\
SRI                70 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\
SRI                71 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\
SRI                72 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\
SRI                73 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\
SRI                74 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\
SRI                75 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\
SRI                76 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\
SRI                77 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\
SRI                78 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(CONTROL, VTG, inst),\
SRI                79 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\
SRI                80 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_MASTER_UPDATE_MODE, OTG, inst),\
SRI                81 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_GSL_CONTROL, OTG, inst),\
SRI                82 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_CRC_CNTL, OTG, inst),\
SRI                83 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_CRC0_DATA_RG, OTG, inst),\
SRI                84 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_CRC0_DATA_B, OTG, inst),\
SRI                85 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\
SRI                86 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
SRI                87 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
SRI                88 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
SRI                90 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
SRI                91 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst)
SRI                95 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_TEST_PATTERN_PARAMETERS, OTG, inst),\
SRI                96 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_TEST_PATTERN_CONTROL, OTG, inst),\
SRI                97 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_TEST_PATTERN_COLOR, OTG, inst),\
SRI                98 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst)
SRI               304 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
SRI                35 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(AFMT_CNTL, DIG, id), \
SRI                36 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(AFMT_GENERIC_0, DIG, id), \
SRI                37 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(AFMT_GENERIC_1, DIG, id), \
SRI                38 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(AFMT_GENERIC_2, DIG, id), \
SRI                39 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(AFMT_GENERIC_3, DIG, id), \
SRI                40 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(AFMT_GENERIC_4, DIG, id), \
SRI                41 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(AFMT_GENERIC_5, DIG, id), \
SRI                42 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(AFMT_GENERIC_6, DIG, id), \
SRI                43 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(AFMT_GENERIC_7, DIG, id), \
SRI                44 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(AFMT_GENERIC_HDR, DIG, id), \
SRI                45 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(AFMT_INFOFRAME_CONTROL0, DIG, id), \
SRI                46 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(AFMT_VBI_PACKET_CONTROL, DIG, id), \
SRI                47 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(AFMT_VBI_PACKET_CONTROL1, DIG, id), \
SRI                48 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(AFMT_AUDIO_PACKET_CONTROL, DIG, id), \
SRI                49 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(AFMT_AUDIO_PACKET_CONTROL2, DIG, id), \
SRI                50 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(AFMT_AUDIO_SRC_CONTROL, DIG, id), \
SRI                51 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(AFMT_60958_0, DIG, id), \
SRI                52 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(AFMT_60958_1, DIG, id), \
SRI                53 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(AFMT_60958_2, DIG, id), \
SRI                54 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(DIG_FE_CNTL, DIG, id), \
SRI                55 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(HDMI_CONTROL, DIG, id), \
SRI                56 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(HDMI_DB_CONTROL, DIG, id), \
SRI                57 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(HDMI_GC, DIG, id), \
SRI                58 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \
SRI                59 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \
SRI                60 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \
SRI                61 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \
SRI                62 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \
SRI                63 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \
SRI                64 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \
SRI                65 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\
SRI                66 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
SRI                67 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(HDMI_ACR_32_0, DIG, id),\
SRI                68 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(HDMI_ACR_32_1, DIG, id),\
SRI                69 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(HDMI_ACR_44_0, DIG, id),\
SRI                70 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(HDMI_ACR_44_1, DIG, id),\
SRI                71 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(HDMI_ACR_48_0, DIG, id),\
SRI                72 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(HDMI_ACR_48_1, DIG, id),\
SRI                73 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(DP_DB_CNTL, DP, id), \
SRI                74 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(DP_MSA_MISC, DP, id), \
SRI                75 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(DP_MSA_COLORIMETRY, DP, id), \
SRI                76 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(DP_MSA_TIMING_PARAM1, DP, id), \
SRI                77 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(DP_MSA_TIMING_PARAM2, DP, id), \
SRI                78 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(DP_MSA_TIMING_PARAM3, DP, id), \
SRI                79 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(DP_MSA_TIMING_PARAM4, DP, id), \
SRI                80 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(DP_MSE_RATE_CNTL, DP, id), \
SRI                81 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(DP_MSE_RATE_UPDATE, DP, id), \
SRI                82 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(DP_PIXEL_FORMAT, DP, id), \
SRI                83 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(DP_SEC_CNTL, DP, id), \
SRI                84 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(DP_SEC_CNTL2, DP, id), \
SRI                85 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(DP_SEC_CNTL6, DP, id), \
SRI                86 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(DP_STEER_FIFO, DP, id), \
SRI                87 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(DP_VID_M, DP, id), \
SRI                88 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(DP_VID_N, DP, id), \
SRI                89 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(DP_VID_STREAM_CNTL, DP, id), \
SRI                90 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(DP_VID_TIMING, DP, id), \
SRI                91 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(DP_SEC_AUD_N, DP, id), \
SRI                92 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(DP_SEC_TIMESTAMP, DP, id), \
SRI                93 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(DIG_CLOCK_PATTERN, DIG, id)
SRI                35 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_LUT_WRITE_EN_MASK, CM, id), \
SRI                36 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_CONTROL, CM, id), \
SRI                37 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMB_START_CNTL_B, CM, id), \
SRI                38 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMB_START_CNTL_G, CM, id), \
SRI                39 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMB_START_CNTL_R, CM, id), \
SRI                40 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_B, CM, id), \
SRI                41 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_G, CM, id), \
SRI                42 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_R, CM, id), \
SRI                43 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMB_END_CNTL1_B, CM, id), \
SRI                44 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMB_END_CNTL2_B, CM, id), \
SRI                45 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMB_END_CNTL1_G, CM, id), \
SRI                46 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMB_END_CNTL2_G, CM, id), \
SRI                47 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMB_END_CNTL1_R, CM, id), \
SRI                48 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMB_END_CNTL2_R, CM, id), \
SRI                49 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMB_REGION_0_1, CM, id), \
SRI                50 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMB_REGION_2_3, CM, id), \
SRI                51 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMB_REGION_4_5, CM, id), \
SRI                52 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMB_REGION_6_7, CM, id), \
SRI                53 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMB_REGION_8_9, CM, id), \
SRI                54 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMB_REGION_10_11, CM, id), \
SRI                55 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMB_REGION_12_13, CM, id), \
SRI                56 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMB_REGION_14_15, CM, id), \
SRI                57 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMB_REGION_16_17, CM, id), \
SRI                58 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMB_REGION_18_19, CM, id), \
SRI                59 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMB_REGION_20_21, CM, id), \
SRI                60 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMB_REGION_22_23, CM, id), \
SRI                61 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMB_REGION_24_25, CM, id), \
SRI                62 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMB_REGION_26_27, CM, id), \
SRI                63 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMB_REGION_28_29, CM, id), \
SRI                64 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMB_REGION_30_31, CM, id), \
SRI                65 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMB_REGION_32_33, CM, id), \
SRI                66 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMA_START_CNTL_B, CM, id), \
SRI                67 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMA_START_CNTL_G, CM, id), \
SRI                68 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMA_START_CNTL_R, CM, id), \
SRI                69 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_B, CM, id), \
SRI                70 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_G, CM, id), \
SRI                71 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_R, CM, id), \
SRI                72 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMA_END_CNTL1_B, CM, id), \
SRI                73 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMA_END_CNTL2_B, CM, id), \
SRI                74 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMA_END_CNTL1_G, CM, id), \
SRI                75 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMA_END_CNTL2_G, CM, id), \
SRI                76 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMA_END_CNTL1_R, CM, id), \
SRI                77 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMA_END_CNTL2_R, CM, id), \
SRI                78 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMA_REGION_0_1, CM, id), \
SRI                79 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMA_REGION_2_3, CM, id), \
SRI                80 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMA_REGION_4_5, CM, id), \
SRI                81 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMA_REGION_6_7, CM, id), \
SRI                82 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMA_REGION_8_9, CM, id), \
SRI                83 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMA_REGION_10_11, CM, id), \
SRI                84 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMA_REGION_12_13, CM, id), \
SRI                85 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMA_REGION_14_15, CM, id), \
SRI                86 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMA_REGION_16_17, CM, id), \
SRI                87 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMA_REGION_18_19, CM, id), \
SRI                88 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMA_REGION_20_21, CM, id), \
SRI                89 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMA_REGION_22_23, CM, id), \
SRI                90 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMA_REGION_24_25, CM, id), \
SRI                91 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMA_REGION_26_27, CM, id), \
SRI                92 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMA_REGION_28_29, CM, id), \
SRI                93 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMA_REGION_30_31, CM, id), \
SRI                94 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_RAMA_REGION_32_33, CM, id), \
SRI                95 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_LUT_INDEX, CM, id), \
SRI                96 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_BLNDGAM_LUT_DATA, CM, id), \
SRI                97 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_3DLUT_MODE, CM, id), \
SRI                98 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_3DLUT_INDEX, CM, id), \
SRI                99 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_3DLUT_DATA, CM, id), \
SRI               100 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_3DLUT_DATA_30BIT, CM, id), \
SRI               101 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_3DLUT_READ_WRITE_CONTROL, CM, id), \
SRI               102 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_LUT_WRITE_EN_MASK, CM, id), \
SRI               103 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_CONTROL, CM, id), \
SRI               104 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMB_START_CNTL_B, CM, id), \
SRI               105 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMB_START_CNTL_G, CM, id), \
SRI               106 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMB_START_CNTL_R, CM, id), \
SRI               107 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMB_END_CNTL_B, CM, id), \
SRI               108 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMB_END_CNTL_G, CM, id), \
SRI               109 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMB_END_CNTL_R, CM, id), \
SRI               110 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMB_REGION_0_1, CM, id), \
SRI               111 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMB_REGION_2_3, CM, id), \
SRI               112 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMB_REGION_4_5, CM, id), \
SRI               113 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMB_REGION_6_7, CM, id), \
SRI               114 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMB_REGION_8_9, CM, id), \
SRI               115 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMB_REGION_10_11, CM, id), \
SRI               116 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMB_REGION_12_13, CM, id), \
SRI               117 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMB_REGION_14_15, CM, id), \
SRI               118 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMB_REGION_16_17, CM, id), \
SRI               119 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMB_REGION_18_19, CM, id), \
SRI               120 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMB_REGION_20_21, CM, id), \
SRI               121 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMB_REGION_22_23, CM, id), \
SRI               122 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMB_REGION_24_25, CM, id), \
SRI               123 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMB_REGION_26_27, CM, id), \
SRI               124 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMB_REGION_28_29, CM, id), \
SRI               125 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMB_REGION_30_31, CM, id), \
SRI               126 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMB_REGION_32_33, CM, id), \
SRI               127 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMA_START_CNTL_B, CM, id), \
SRI               128 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMA_START_CNTL_G, CM, id), \
SRI               129 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMA_START_CNTL_R, CM, id), \
SRI               130 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMA_END_CNTL_B, CM, id), \
SRI               131 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMA_END_CNTL_G, CM, id), \
SRI               132 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMA_END_CNTL_R, CM, id), \
SRI               133 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMA_REGION_0_1, CM, id), \
SRI               134 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMA_REGION_2_3, CM, id), \
SRI               135 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMA_REGION_4_5, CM, id), \
SRI               136 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMA_REGION_6_7, CM, id), \
SRI               137 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMA_REGION_8_9, CM, id), \
SRI               138 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMA_REGION_10_11, CM, id), \
SRI               139 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMA_REGION_12_13, CM, id), \
SRI               140 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMA_REGION_14_15, CM, id), \
SRI               141 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMA_REGION_16_17, CM, id), \
SRI               142 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMA_REGION_18_19, CM, id), \
SRI               143 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMA_REGION_20_21, CM, id), \
SRI               144 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMA_REGION_22_23, CM, id), \
SRI               145 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMA_REGION_24_25, CM, id), \
SRI               146 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMA_REGION_26_27, CM, id), \
SRI               147 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMA_REGION_28_29, CM, id), \
SRI               148 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMA_REGION_30_31, CM, id), \
SRI               149 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_RAMA_REGION_32_33, CM, id), \
SRI               150 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_LUT_INDEX, CM, id), \
SRI               151 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CURSOR_CONTROL, CURSOR0_, id), \
SRI               152 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(ALPHA_2BIT_LUT, CNVC_CFG, id), \
SRI               153 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(FCNV_FP_BIAS_R, CNVC_CFG, id), \
SRI               154 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(FCNV_FP_BIAS_G, CNVC_CFG, id), \
SRI               155 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(FCNV_FP_BIAS_B, CNVC_CFG, id), \
SRI               156 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(FCNV_FP_SCALE_R, CNVC_CFG, id), \
SRI               157 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(FCNV_FP_SCALE_G, CNVC_CFG, id), \
SRI               158 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(FCNV_FP_SCALE_B, CNVC_CFG, id), \
SRI               159 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(COLOR_KEYER_CONTROL, CNVC_CFG, id), \
SRI               160 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(COLOR_KEYER_ALPHA, CNVC_CFG, id), \
SRI               161 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(COLOR_KEYER_RED, CNVC_CFG, id), \
SRI               162 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(COLOR_KEYER_GREEN, CNVC_CFG, id), \
SRI               163 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(COLOR_KEYER_BLUE, CNVC_CFG, id), \
SRI               164 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CM_SHAPER_LUT_DATA, CM, id), \
SRI               165 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(CURSOR_CONTROL, CURSOR0_, id),\
SRI               166 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(OBUF_MEM_PWR_CTRL, DSCL, id),\
SRI               167 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 	SRI(DSCL_MEM_PWR_CTRL, DSCL, id)
SRI                36 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSC_TOP_CONTROL, DSC_TOP, id),\
SRI                37 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSC_DEBUG_CONTROL, DSC_TOP, id),\
SRI                38 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_CONFIG0, DSCC, id),\
SRI                39 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_CONFIG1, DSCC, id),\
SRI                40 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_STATUS, DSCC, id),\
SRI                41 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_INTERRUPT_CONTROL_STATUS, DSCC, id),\
SRI                42 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_PPS_CONFIG0, DSCC, id),\
SRI                43 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_PPS_CONFIG1, DSCC, id),\
SRI                44 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_PPS_CONFIG2, DSCC, id),\
SRI                45 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_PPS_CONFIG3, DSCC, id),\
SRI                46 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_PPS_CONFIG4, DSCC, id),\
SRI                47 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_PPS_CONFIG5, DSCC, id),\
SRI                48 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_PPS_CONFIG6, DSCC, id),\
SRI                49 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_PPS_CONFIG7, DSCC, id),\
SRI                50 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_PPS_CONFIG8, DSCC, id),\
SRI                51 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_PPS_CONFIG9, DSCC, id),\
SRI                52 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_PPS_CONFIG10, DSCC, id),\
SRI                53 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_PPS_CONFIG11, DSCC, id),\
SRI                54 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_PPS_CONFIG12, DSCC, id),\
SRI                55 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_PPS_CONFIG13, DSCC, id),\
SRI                56 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_PPS_CONFIG14, DSCC, id),\
SRI                57 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_PPS_CONFIG15, DSCC, id),\
SRI                58 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_PPS_CONFIG16, DSCC, id),\
SRI                59 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_PPS_CONFIG17, DSCC, id),\
SRI                60 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_PPS_CONFIG18, DSCC, id),\
SRI                61 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_PPS_CONFIG19, DSCC, id),\
SRI                62 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_PPS_CONFIG20, DSCC, id),\
SRI                63 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_PPS_CONFIG21, DSCC, id),\
SRI                64 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_PPS_CONFIG22, DSCC, id),\
SRI                65 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_MEM_POWER_CONTROL, DSCC, id),\
SRI                66 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_R_Y_SQUARED_ERROR_LOWER, DSCC, id),\
SRI                67 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_R_Y_SQUARED_ERROR_UPPER, DSCC, id),\
SRI                68 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_G_CB_SQUARED_ERROR_LOWER, DSCC, id),\
SRI                69 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_G_CB_SQUARED_ERROR_UPPER, DSCC, id),\
SRI                70 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_B_CR_SQUARED_ERROR_LOWER, DSCC, id),\
SRI                71 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_B_CR_SQUARED_ERROR_UPPER, DSCC, id),\
SRI                72 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_MAX_ABS_ERROR0, DSCC, id),\
SRI                73 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_MAX_ABS_ERROR1, DSCC, id),\
SRI                74 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL, DSCC, id),\
SRI                75 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL, DSCC, id),\
SRI                76 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL, DSCC, id),\
SRI                77 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL, DSCC, id),\
SRI                78 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL, DSCC, id),\
SRI                79 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, DSCC, id),\
SRI                80 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, DSCC, id),\
SRI                81 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, DSCC, id),\
SRI                82 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCC_TEST_DEBUG_BUS_ROTATE, DSCC, id),\
SRI                83 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCCIF_CONFIG0, DSCCIF, id),\
SRI                84 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCCIF_CONFIG1, DSCCIF, id),\
SRI                85 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h 	SRI(DSCRM_DSC_FORWARD_CONFIG, DSCRM, id)
SRI                37 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h 	SRI(PREFETCH_SETTINGS, HUBPREQ, id),\
SRI                38 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h 	SRI(PREFETCH_SETTINGS_C, HUBPREQ, id),\
SRI                39 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h 	SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, HUBPREQ, id),\
SRI                40 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h 	SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, HUBPREQ, id),\
SRI                41 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h 	SRI(CURSOR_SETTINGS, HUBPREQ, id), \
SRI                42 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h 	SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id), \
SRI                43 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h 	SRI(CURSOR_SURFACE_ADDRESS, CURSOR0_, id), \
SRI                44 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h 	SRI(CURSOR_SIZE, CURSOR0_, id), \
SRI                45 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h 	SRI(CURSOR_CONTROL, CURSOR0_, id), \
SRI                46 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h 	SRI(CURSOR_POSITION, CURSOR0_, id), \
SRI                47 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h 	SRI(CURSOR_HOT_SPOT, CURSOR0_, id), \
SRI                48 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h 	SRI(CURSOR_DST_OFFSET, CURSOR0_, id), \
SRI                49 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h 	SRI(DMDATA_ADDRESS_HIGH, CURSOR0_, id), \
SRI                50 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h 	SRI(DMDATA_ADDRESS_LOW, CURSOR0_, id), \
SRI                51 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h 	SRI(DMDATA_CNTL, CURSOR0_, id), \
SRI                52 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h 	SRI(DMDATA_SW_CNTL, CURSOR0_, id), \
SRI                53 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h 	SRI(DMDATA_QOS_CNTL, CURSOR0_, id), \
SRI                54 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h 	SRI(DMDATA_SW_DATA, CURSOR0_, id), \
SRI                55 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h 	SRI(DMDATA_STATUS, CURSOR0_, id),\
SRI                56 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h 	SRI(FLIP_PARAMETERS_0, HUBPREQ, id),\
SRI                57 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h 	SRI(FLIP_PARAMETERS_1, HUBPREQ, id),\
SRI                58 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h 	SRI(FLIP_PARAMETERS_2, HUBPREQ, id),\
SRI                59 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h 	SRI(DCN_CUR1_TTU_CNTL0, HUBPREQ, id),\
SRI                60 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h 	SRI(DCN_CUR1_TTU_CNTL1, HUBPREQ, id),\
SRI                61 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h 	SRI(DCSURF_FLIP_CONTROL2, HUBPREQ, id), \
SRI                62 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h 	SRI(VMID_SETTINGS_0, HUBPREQ, id)
SRI                33 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h 	SRI(AUX_DPHY_TX_CONTROL, DP_AUX, id)
SRI                63 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h 	SRI(CLOCK_ENABLE, SYMCLK, id), \
SRI                64 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h 	SRI(CHANNEL_XBAR_CNTL, UNIPHY, id)
SRI                60 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
SRI                61 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUFMGR_CUR_LINE_R, MCIF_WB, inst),\
SRI                62 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst),\
SRI                63 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
SRI                64 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst),\
SRI                65 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst),\
SRI                66 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst),\
SRI                67 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst),\
SRI                68 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst),\
SRI                69 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst),\
SRI                70 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_4_STATUS, MCIF_WB, inst),\
SRI                71 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_4_STATUS2, MCIF_WB, inst),\
SRI                72 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\
SRI                73 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\
SRI                74 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_TEST_DEBUG_INDEX, MCIF_WB, inst),\
SRI                75 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_TEST_DEBUG_DATA, MCIF_WB, inst),\
SRI                76 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\
SRI                77 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB, inst),\
SRI                78 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\
SRI                79 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB, inst),\
SRI                80 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\
SRI                81 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB, inst),\
SRI                82 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\
SRI                83 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB, inst),\
SRI                84 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\
SRI                85 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB, inst),\
SRI                86 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\
SRI                87 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB, inst),\
SRI                88 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\
SRI                89 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB, inst),\
SRI                90 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\
SRI                91 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB, inst),\
SRI                92 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\
SRI                93 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MCIF_WB, inst),\
SRI                94 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\
SRI                95 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_WATERMARK, MCIF_WB, inst),\
SRI                96 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB, inst),\
SRI                97 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_WARM_UP_CNTL, MCIF_WB, inst),\
SRI                98 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_SELF_REFRESH_CONTROL, MCIF_WB, inst),\
SRI                99 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MULTI_LEVEL_QOS_CTRL, MCIF_WB, inst),\
SRI               100 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_SECURITY_LEVEL, MCIF_WB, inst),\
SRI               101 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\
SRI               102 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst),\
SRI               103 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB, inst),\
SRI               104 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB, inst),\
SRI               105 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB, inst),\
SRI               106 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB, inst),\
SRI               107 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB, inst),\
SRI               108 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB, inst),\
SRI               109 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB, inst),\
SRI               110 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB, inst),\
SRI               111 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_1_RESOLUTION, MCIF_WB, inst),\
SRI               112 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_2_RESOLUTION, MCIF_WB, inst),\
SRI               113 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_3_RESOLUTION, MCIF_WB, inst),\
SRI               114 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_4_RESOLUTION, MCIF_WB, inst),\
SRI               115 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(SMU_WM_CONTROL, WBIF, inst)
SRI                37 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h 	SRI(DPG_CONTROL, DPG, id), \
SRI                38 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h 	SRI(DPG_DIMENSIONS, DPG, id), \
SRI                39 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h 	SRI(DPG_COLOUR_B_CB, DPG, id), \
SRI                40 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h 	SRI(DPG_COLOUR_G_Y, DPG, id), \
SRI                41 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h 	SRI(DPG_COLOUR_R_CR, DPG, id), \
SRI                42 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h 	SRI(DPG_RAMP_CONTROL, DPG, id), \
SRI                43 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h 	SRI(DPG_STATUS, DPG, id)
SRI                48 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h 	SRI(FMT_422_CONTROL, FMT, id), \
SRI                49 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h 	SRI(OPPBUF_CONTROL1, OPPBUF, id)
SRI                33 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h 	SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
SRI                34 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h 	SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
SRI                35 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h 	SRI(OTG_GSL_WINDOW_X, OTG, inst),\
SRI                36 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h 	SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
SRI                37 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h 	SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
SRI                38 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h 	SRI(OTG_DSC_START_POSITION, OTG, inst),\
SRI                39 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h 	SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\
SRI                40 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h 	SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\
SRI                41 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h 	SRI(OPTC_WIDTH_CONTROL, ODM, inst),\
SRI                42 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h 	SRI(OPTC_MEMORY_CONFIG, ODM, inst),\
SRI                44 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h 	SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst)
SRI               599 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
SRI                35 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h 	SRI(HDMI_GENERIC_PACKET_CONTROL4, DIG, id), \
SRI                36 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h 	SRI(HDMI_GENERIC_PACKET_CONTROL5, DIG, id), \
SRI                37 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h 	SRI(DP_DSC_CNTL, DP, id), \
SRI                38 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h 	SRI(DP_DSC_BYTES_PER_PIXEL, DP, id), \
SRI                39 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h 	SRI(DME_CONTROL, DIG, id),\
SRI                40 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h 	SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \
SRI                41 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h 	SRI(HDMI_METADATA_PACKET_CONTROL, DIG, id), \
SRI                42 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h 	SRI(DP_SEC_FRAMING4, DP, id)
SRI                45 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h 	SRI(CNTL, DCN_VM_CONTEXT, id),\
SRI                46 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h 	SRI(PAGE_TABLE_BASE_ADDR_HI32, DCN_VM_CONTEXT, id),\
SRI                47 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h 	SRI(PAGE_TABLE_BASE_ADDR_LO32, DCN_VM_CONTEXT, id),\
SRI                48 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h 	SRI(PAGE_TABLE_START_ADDR_HI32, DCN_VM_CONTEXT, id),\
SRI                49 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h 	SRI(PAGE_TABLE_START_ADDR_LO32, DCN_VM_CONTEXT, id),\
SRI                50 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h 	SRI(PAGE_TABLE_END_ADDR_HI32, DCN_VM_CONTEXT, id),\
SRI                51 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h 	SRI(PAGE_TABLE_END_ADDR_LO32, DCN_VM_CONTEXT, id)
SRI                37 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h 	SRI(FLIP_PARAMETERS_3, HUBPREQ, id),\
SRI                38 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h 	SRI(FLIP_PARAMETERS_4, HUBPREQ, id),\
SRI                39 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h 	SRI(FLIP_PARAMETERS_5, HUBPREQ, id),\
SRI                40 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h 	SRI(FLIP_PARAMETERS_6, HUBPREQ, id),\
SRI                41 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h 	SRI(VBLANK_PARAMETERS_5, HUBPREQ, id),\
SRI                42 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h 	SRI(VBLANK_PARAMETERS_6, HUBPREQ, id)
SRI               106 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c 	.enable_reg = SRI(reg1, block, reg_num),\
SRI               113 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c 	.ack_reg = SRI(reg2, block, reg_num),\
SRI               124 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c 		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
SRI               133 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c 		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
SRI               141 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c 		.status_reg = SRI(GRPH_INTERRUPT_STATUS, DCP, reg_num),\
SRI               187 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c 	.enable_reg = SRI(reg1, block, reg_num),\
SRI               194 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c 	.ack_reg = SRI(reg2, block, reg_num),\
SRI               205 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c 		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
SRI               214 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c 		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
SRI               189 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c 	.enable_reg = SRI(reg1, block, reg_num),\
SRI               196 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c 	.ack_reg = SRI(reg2, block, reg_num),\
SRI               209 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c 		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
SRI               218 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c 		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
SRI               185 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c 	.enable_reg = SRI(reg1, block, reg_num),\
SRI               192 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c 	.ack_reg = SRI(reg2, block, reg_num),\
SRI               205 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c 		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
SRI               214 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c 		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\