SRCC0             165 arch/sh/kernel/cpu/sh2a/setup-sh7264.c 	INTC_IRQ(SRCC0, 299), INTC_IRQ(SRCC0, 300),
SRCC0             166 arch/sh/kernel/cpu/sh2a/setup-sh7264.c 	INTC_IRQ(SRCC0, 301), INTC_IRQ(SRCC0, 302),
SRCC0             167 arch/sh/kernel/cpu/sh2a/setup-sh7264.c 	INTC_IRQ(SRCC0, 303),
SRCC0             213 arch/sh/kernel/cpu/sh2a/setup-sh7264.c 	{ 0xfffe0c20, 0, 16, 4, /* IPR22 */ { SRCC0, SRCC1, 0, DCOMU } },
SRCC0             182 arch/sh/kernel/cpu/sh2a/setup-sh7269.c 	INTC_IRQ(SRCC0, 341), INTC_IRQ(SRCC0, 342),
SRCC0             183 arch/sh/kernel/cpu/sh2a/setup-sh7269.c 	INTC_IRQ(SRCC0, 343), INTC_IRQ(SRCC0, 344),
SRCC0             184 arch/sh/kernel/cpu/sh2a/setup-sh7269.c 	INTC_IRQ(SRCC0, 345),
SRCC0             235 arch/sh/kernel/cpu/sh2a/setup-sh7269.c 	{ 0xfffe0c28, 0, 16, 4, /* IPR26 */ { SRCC0, SRCC1, SRCC2, 0 } },