SR 104 arch/alpha/math-emu/math.c FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR); SR 138 arch/alpha/math-emu/math.c FP_SUB_S(SR, SA, SB); SR 142 arch/alpha/math-emu/math.c FP_ADD_S(SR, SA, SB); SR 146 arch/alpha/math-emu/math.c FP_MUL_S(SR, SA, SB); SR 150 arch/alpha/math-emu/math.c FP_DIV_S(SR, SA, SB); SR 154 arch/alpha/math-emu/math.c FP_SQRT_S(SR, SB); SR 224 arch/alpha/math-emu/math.c FP_CONV(S,D,1,1,SR,DB); SR 262 arch/alpha/math-emu/math.c FP_FROM_INT_S(SR, ((long)vb), 64, long); SR 274 arch/alpha/math-emu/math.c FP_PACK_SP(&vc, SR); SR 215 arch/powerpc/math-emu/math_efp.c FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR); SR 246 arch/powerpc/math-emu/math_efp.c FP_ADD_S(SR, SA, SB); SR 250 arch/powerpc/math-emu/math_efp.c FP_SUB_S(SR, SA, SB); SR 254 arch/powerpc/math-emu/math_efp.c FP_MUL_S(SR, SA, SB); SR 258 arch/powerpc/math-emu/math_efp.c FP_DIV_S(SR, SA, SB); SR 293 arch/powerpc/math-emu/math_efp.c FP_CONV(S, D, 1, 2, SR, DB); SR 327 arch/powerpc/math-emu/math_efp.c FP_PACK_SP(vc.wp + 1, SR); SR 676 arch/powerpc/xmon/ppc-opc.c #define UIMM4 SR SR 680 arch/powerpc/xmon/ppc-opc.c #define STRM SR + 1 SR 4845 arch/powerpc/xmon/ppc-opc.c {"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, 0, {SR, RS}}, SR 4997 arch/powerpc/xmon/ppc-opc.c {"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}}, SR 5840 arch/powerpc/xmon/ppc-opc.c {"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}}, SR 84 arch/sh/include/cpu-sh5/cpu/registers.h #define __SR __str(SR) SR 286 arch/sparc/math-emu/math_32.c FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR); SR 428 arch/sparc/math-emu/math_32.c case FADDS: FP_ADD_S (SR, SA, SB); break; SR 432 arch/sparc/math-emu/math_32.c case FSUBS: FP_SUB_S (SR, SA, SB); break; SR 436 arch/sparc/math-emu/math_32.c case FMULS: FP_MUL_S (SR, SA, SB); break; SR 444 arch/sparc/math-emu/math_32.c case FDIVS: FP_DIV_S (SR, SA, SB); break; SR 448 arch/sparc/math-emu/math_32.c case FSQRTS: FP_SQRT_S (SR, SB); break; SR 460 arch/sparc/math-emu/math_32.c case FITOS: IR = rs2->s; FP_FROM_INT_S (SR, IR, 32, int); break; SR 467 arch/sparc/math-emu/math_32.c case FDTOS: FP_CONV (S, D, 1, 2, SR, DB); break; SR 468 arch/sparc/math-emu/math_32.c case FQTOS: FP_CONV (S, Q, 1, 4, SR, QB); break; SR 507 arch/sparc/math-emu/math_32.c case 5: FP_PACK_SP (rd, SR); break; SR 181 arch/sparc/math-emu/math_64.c FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR); SR 433 arch/sparc/math-emu/math_64.c case FADDS: FP_ADD_S (SR, SA, SB); break; SR 437 arch/sparc/math-emu/math_64.c case FSUBS: FP_SUB_S (SR, SA, SB); break; SR 441 arch/sparc/math-emu/math_64.c case FMULS: FP_MUL_S (SR, SA, SB); break; SR 449 arch/sparc/math-emu/math_64.c case FDIVS: FP_DIV_S (SR, SA, SB); break; SR 453 arch/sparc/math-emu/math_64.c case FSQRTS: FP_SQRT_S (SR, SB); break; SR 471 arch/sparc/math-emu/math_64.c case FXTOS: XR = rs2->d; FP_FROM_INT_S (SR, XR, 64, long); break; SR 474 arch/sparc/math-emu/math_64.c case FITOS: IR = rs2->s; FP_FROM_INT_S (SR, IR, 32, int); break; SR 481 arch/sparc/math-emu/math_64.c case FDTOS: FP_CONV (S, D, 1, 1, SR, DB); break; SR 482 arch/sparc/math-emu/math_64.c case FQTOS: FP_CONV (S, Q, 1, 2, SR, QB); break; SR 509 arch/sparc/math-emu/math_64.c case 5: FP_PACK_SP (rd, SR); break; SR 78 drivers/clocksource/timer-atmel-tcb.c tcb_cache[i].clken = !!(readl(tcaddr + ATMEL_TC_REG(i, SR)) & SR 250 drivers/clocksource/timer-atmel-tcb.c sr = readl_relaxed(dev->regs + ATMEL_TC_REG(2, SR)); SR 33 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h SR(BL_PWM_PERIOD_CNTL), \ SR 34 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h SR(BL_PWM_CNTL), \ SR 35 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h SR(BL_PWM_CNTL2), \ SR 36 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h SR(BL_PWM_GRP1_REG_LOCK), \ SR 37 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h SR(LVTMA_PWRSEQ_REF_DIV), \ SR 38 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h SR(MASTER_COMM_CNTL_REG), \ SR 39 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h SR(MASTER_COMM_CMD_REG), \ SR 40 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h SR(MASTER_COMM_DATA_REG1) SR 44 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h SR(DC_ABM1_HG_SAMPLE_RATE), \ SR 45 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h SR(DC_ABM1_LS_SAMPLE_RATE), \ SR 46 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \ SR 47 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h SR(DC_ABM1_HG_MISC_CTRL), \ SR 48 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h SR(DC_ABM1_IPCSC_COEFF_SEL), \ SR 49 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h SR(BL1_PWM_CURRENT_ABM_LEVEL), \ SR 50 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h SR(BL1_PWM_TARGET_ABM_LEVEL), \ SR 51 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h SR(BL1_PWM_USER_LEVEL), \ SR 52 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \ SR 53 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \ SR 54 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h SR(BIOS_SCRATCH_2) SR 73 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h SR(DC_ABM1_HG_SAMPLE_RATE), \ SR 74 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h SR(DC_ABM1_LS_SAMPLE_RATE), \ SR 75 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \ SR 76 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h SR(DC_ABM1_HG_MISC_CTRL), \ SR 77 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h SR(DC_ABM1_IPCSC_COEFF_SEL), \ SR 78 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h SR(BL1_PWM_CURRENT_ABM_LEVEL), \ SR 79 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h SR(BL1_PWM_TARGET_ABM_LEVEL), \ SR 80 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h SR(BL1_PWM_USER_LEVEL), \ SR 81 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \ SR 82 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \ SR 33 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS),\ SR 34 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES),\ SR 35 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES),\ SR 36 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h SR(DCCG_AUDIO_DTO_SOURCE),\ SR 37 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h SR(DCCG_AUDIO_DTO0_MODULE),\ SR 38 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h SR(DCCG_AUDIO_DTO0_PHASE),\ SR 39 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h SR(DCCG_AUDIO_DTO1_MODULE),\ SR 40 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h SR(DCCG_AUDIO_DTO1_PHASE) SR 49 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h SR(AUXN_IMPCAL), \ SR 50 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h SR(AUXP_IMPCAL) SR 33 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h SR(DMCU_CTRL), \ SR 34 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h SR(DMCU_STATUS), \ SR 35 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h SR(DMCU_RAM_ACCESS_CTRL), \ SR 36 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h SR(DMCU_IRAM_WR_CTRL), \ SR 37 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h SR(DMCU_IRAM_WR_DATA), \ SR 38 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h SR(MASTER_COMM_DATA_REG1), \ SR 39 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h SR(MASTER_COMM_DATA_REG2), \ SR 40 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h SR(MASTER_COMM_DATA_REG3), \ SR 41 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h SR(MASTER_COMM_CMD_REG), \ SR 42 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h SR(MASTER_COMM_CNTL_REG), \ SR 43 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h SR(DMCU_IRAM_RD_CTRL), \ SR 44 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h SR(DMCU_IRAM_RD_DATA), \ SR 45 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \ SR 46 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h SR(SMU_INTERRUPT_CONTROL), \ SR 47 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h SR(DC_DMCU_SCRATCH) SR 50 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h SR(DMCU_CTRL), \ SR 51 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h SR(DMCU_STATUS), \ SR 52 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h SR(DMCU_RAM_ACCESS_CTRL), \ SR 53 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h SR(DMCU_IRAM_WR_CTRL), \ SR 54 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h SR(DMCU_IRAM_WR_DATA), \ SR 55 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h SR(MASTER_COMM_DATA_REG1), \ SR 56 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h SR(MASTER_COMM_DATA_REG2), \ SR 57 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h SR(MASTER_COMM_DATA_REG3), \ SR 58 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h SR(MASTER_COMM_CMD_REG), \ SR 59 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h SR(MASTER_COMM_CNTL_REG), \ SR 60 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h SR(DMCU_IRAM_RD_CTRL), \ SR 61 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h SR(DMCU_IRAM_RD_DATA), \ SR 62 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \ SR 63 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h SR(SMU_INTERRUPT_CONTROL), \ SR 64 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h SR(DC_DMCU_SCRATCH) SR 68 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h SR(DCI_MEM_PWR_STATUS) SR 72 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h SR(DMU_MEM_PWR_CNTL) SR 31 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(LVTMA_PWRSEQ_CNTL), \ SR 32 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(LVTMA_PWRSEQ_STATE) SR 49 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DC_MEM_GLOBAL_PWR_REQ_CNTL) SR 86 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ SR 87 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DCFEV_CLOCK_CONTROL), \ SR 96 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(BLNDV_CONTROL),\ SR 134 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DCHUB_FB_LOCATION),\ SR 135 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DCHUB_AGP_BASE),\ SR 136 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DCHUB_AGP_BOT),\ SR 137 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DCHUB_AGP_TOP), \ SR 151 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(REFCLK_CNTL), \ SR 152 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ SR 153 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DIO_MEM_PWR_CTRL), \ SR 154 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DCCG_GATE_DISABLE_CNTL), \ SR 155 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DCCG_GATE_DISABLE_CNTL2), \ SR 156 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DCFCLK_CNTL),\ SR 157 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DCFCLK_CNTL), \ SR 158 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DC_MEM_GLOBAL_PWR_REQ_CNTL) SR 184 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DCHUBBUB_SDPIF_FB_BASE),\ SR 185 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DCHUBBUB_SDPIF_FB_OFFSET),\ SR 186 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DCHUBBUB_SDPIF_AGP_BASE),\ SR 187 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DCHUBBUB_SDPIF_AGP_BOT),\ SR 188 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DCHUBBUB_SDPIF_AGP_TOP),\ SR 189 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN0_PG_CONFIG), \ SR 190 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN1_PG_CONFIG), \ SR 191 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN2_PG_CONFIG), \ SR 192 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN3_PG_CONFIG), \ SR 193 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN4_PG_CONFIG), \ SR 194 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN5_PG_CONFIG), \ SR 195 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN6_PG_CONFIG), \ SR 196 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN7_PG_CONFIG), \ SR 197 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN0_PG_STATUS), \ SR 198 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN1_PG_STATUS), \ SR 199 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN2_PG_STATUS), \ SR 200 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN3_PG_STATUS), \ SR 201 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN4_PG_STATUS), \ SR 202 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN5_PG_STATUS), \ SR 203 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN6_PG_STATUS), \ SR 204 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN7_PG_STATUS), \ SR 205 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(D1VGA_CONTROL), \ SR 206 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(D2VGA_CONTROL), \ SR 207 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(D3VGA_CONTROL), \ SR 208 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(D4VGA_CONTROL), \ SR 209 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(VGA_TEST_CONTROL), \ SR 210 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DC_IP_REQUEST_CNTL), \ SR 222 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(MICROSECOND_TIME_BASE_DIV), \ SR 223 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(MILLISECOND_TIME_BASE_DIV), \ SR 224 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DISPCLK_FREQ_CHANGE_CNTL), \ SR 225 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(RBBMIF_TIMEOUT_DIS), \ SR 226 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(RBBMIF_TIMEOUT_DIS_2), \ SR 227 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DCHUBBUB_CRC_CTRL), \ SR 228 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DPP_TOP0_DPP_CRC_CTRL), \ SR 229 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ SR 230 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ SR 231 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(MPC_CRC_CTRL), \ SR 232 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(MPC_CRC_RESULT_GB), \ SR 233 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(MPC_CRC_RESULT_C), \ SR 234 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(MPC_CRC_RESULT_AR), \ SR 235 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN0_PG_CONFIG), \ SR 236 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN1_PG_CONFIG), \ SR 237 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN2_PG_CONFIG), \ SR 238 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN3_PG_CONFIG), \ SR 239 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN4_PG_CONFIG), \ SR 240 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN5_PG_CONFIG), \ SR 241 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN6_PG_CONFIG), \ SR 242 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN7_PG_CONFIG), \ SR 243 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN8_PG_CONFIG), \ SR 244 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN9_PG_CONFIG), \ SR 247 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN16_PG_CONFIG), \ SR 248 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN17_PG_CONFIG), \ SR 249 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN18_PG_CONFIG), \ SR 250 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN19_PG_CONFIG), \ SR 251 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN20_PG_CONFIG), \ SR 252 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN21_PG_CONFIG), \ SR 253 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN0_PG_STATUS), \ SR 254 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN1_PG_STATUS), \ SR 255 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN2_PG_STATUS), \ SR 256 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN3_PG_STATUS), \ SR 257 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN4_PG_STATUS), \ SR 258 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN5_PG_STATUS), \ SR 259 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN6_PG_STATUS), \ SR 260 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN7_PG_STATUS), \ SR 261 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN8_PG_STATUS), \ SR 262 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN9_PG_STATUS), \ SR 263 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN10_PG_STATUS), \ SR 264 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN11_PG_STATUS), \ SR 265 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN16_PG_STATUS), \ SR 266 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN17_PG_STATUS), \ SR 267 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN18_PG_STATUS), \ SR 268 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN19_PG_STATUS), \ SR 269 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN20_PG_STATUS), \ SR 270 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN21_PG_STATUS), \ SR 271 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(D1VGA_CONTROL), \ SR 272 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(D2VGA_CONTROL), \ SR 273 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(D3VGA_CONTROL), \ SR 274 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(D4VGA_CONTROL), \ SR 275 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(D5VGA_CONTROL), \ SR 276 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(D6VGA_CONTROL), \ SR 277 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DC_IP_REQUEST_CNTL), \ SR 289 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(MICROSECOND_TIME_BASE_DIV), \ SR 290 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(MILLISECOND_TIME_BASE_DIV), \ SR 291 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DISPCLK_FREQ_CHANGE_CNTL), \ SR 292 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(RBBMIF_TIMEOUT_DIS), \ SR 293 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(RBBMIF_TIMEOUT_DIS_2), \ SR 294 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DCHUBBUB_CRC_CTRL), \ SR 295 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DPP_TOP0_DPP_CRC_CTRL), \ SR 296 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ SR 297 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ SR 298 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(MPC_CRC_CTRL), \ SR 299 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(MPC_CRC_RESULT_GB), \ SR 300 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(MPC_CRC_RESULT_C), \ SR 301 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(MPC_CRC_RESULT_AR), \ SR 302 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN0_PG_CONFIG), \ SR 303 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN1_PG_CONFIG), \ SR 304 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN2_PG_CONFIG), \ SR 305 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN3_PG_CONFIG), \ SR 306 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN4_PG_CONFIG), \ SR 307 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN5_PG_CONFIG), \ SR 308 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN6_PG_CONFIG), \ SR 309 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN7_PG_CONFIG), \ SR 310 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN16_PG_CONFIG), \ SR 311 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN17_PG_CONFIG), \ SR 312 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN18_PG_CONFIG), \ SR 313 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN0_PG_STATUS), \ SR 314 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN1_PG_STATUS), \ SR 315 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN2_PG_STATUS), \ SR 316 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN3_PG_STATUS), \ SR 317 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN4_PG_STATUS), \ SR 318 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN5_PG_STATUS), \ SR 319 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN6_PG_STATUS), \ SR 320 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN7_PG_STATUS), \ SR 321 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN16_PG_STATUS), \ SR 322 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN17_PG_STATUS), \ SR 323 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DOMAIN18_PG_STATUS), \ SR 324 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(D1VGA_CONTROL), \ SR 325 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(D2VGA_CONTROL), \ SR 326 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(D3VGA_CONTROL), \ SR 327 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(D4VGA_CONTROL), \ SR 328 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(D5VGA_CONTROL), \ SR 329 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(D6VGA_CONTROL), \ SR 330 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DC_IP_REQUEST_CNTL), \ SR 88 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h SR(DC_I2C_ARBITRATION),\ SR 89 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h SR(DC_I2C_CONTROL),\ SR 90 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h SR(DC_I2C_SW_STATUS),\ SR 91 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h SR(DC_I2C_TRANSACTION0),\ SR 92 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h SR(DC_I2C_TRANSACTION1),\ SR 93 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h SR(DC_I2C_TRANSACTION2),\ SR 94 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h SR(DC_I2C_TRANSACTION3),\ SR 95 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h SR(DC_I2C_DATA),\ SR 96 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h SR(MICROSECOND_TIME_BASE_DIV) SR 47 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h SR(DMCU_RAM_ACCESS_CTRL), \ SR 48 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h SR(DMCU_IRAM_RD_CTRL), \ SR 49 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h SR(DMCU_IRAM_RD_DATA), \ SR 50 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \ SR 76 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h SR(DCI_MEM_PWR_STATUS) SR 86 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h SR(DCI_MEM_PWR_STATUS) SR 93 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h SR(DCI_MEM_PWR_STATUS) SR 99 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h SR(DCI_MEM_PWR_STATUS) SR 79 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SR(DCHUB_FB_LOCATION),\ SR 80 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SR(DCHUB_AGP_BASE),\ SR 81 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SR(DCHUB_AGP_BOT),\ SR 82 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SR(DCHUB_AGP_TOP) SR 36 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\ SR 37 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\ SR 38 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\ SR 39 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\ SR 40 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\ SR 41 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\ SR 42 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\ SR 43 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\ SR 44 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\ SR 45 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\ SR 46 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h SR(DCHUBBUB_ARB_SAT_LEVEL),\ SR 47 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\ SR 48 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ SR 49 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h SR(DCHUBBUB_TEST_DEBUG_INDEX), \ SR 50 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h SR(DCHUBBUB_TEST_DEBUG_DATA),\ SR 51 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h SR(DCHUBBUB_SOFT_RESET) SR 54 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A),\ SR 55 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B),\ SR 56 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C),\ SR 57 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D) SR 60 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),\ SR 61 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A),\ SR 62 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B),\ SR 63 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B),\ SR 64 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C),\ SR 65 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C),\ SR 66 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D),\ SR 67 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D) SR 73 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h SR(DCHUBBUB_SDPIF_FB_TOP),\ SR 74 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h SR(DCHUBBUB_SDPIF_FB_BASE),\ SR 75 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h SR(DCHUBBUB_SDPIF_FB_OFFSET),\ SR 76 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h SR(DCHUBBUB_SDPIF_AGP_BASE),\ SR 77 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h SR(DCHUBBUB_SDPIF_AGP_BOT),\ SR 78 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h SR(DCHUBBUB_SDPIF_AGP_TOP) SR 89 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SR(GSL_SOURCE_SELECT),\ SR 32 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h SR(DPPCLK_DTO_CTRL),\ SR 37 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h SR(REFCLK_CNTL) SR 34 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h SR(DCHUBBUB_CRC_CTRL), \ SR 35 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h SR(DCN_VM_FB_LOCATION_BASE),\ SR 36 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h SR(DCN_VM_FB_LOCATION_TOP),\ SR 37 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h SR(DCN_VM_FB_OFFSET),\ SR 38 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h SR(DCN_VM_AGP_BOT),\ SR 39 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h SR(DCN_VM_AGP_TOP),\ SR 40 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h SR(DCN_VM_AGP_BASE) SR 47 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h SR(DCHUBBUB_CRC_CTRL), \ SR 48 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h SR(DCN_VM_FB_LOCATION_BASE),\ SR 49 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h SR(DCN_VM_FB_LOCATION_TOP),\ SR 50 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h SR(DCN_VM_FB_OFFSET),\ SR 51 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h SR(DCN_VM_AGP_BOT),\ SR 52 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h SR(DCN_VM_AGP_TOP),\ SR 53 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h SR(DCN_VM_AGP_BASE) SR 59 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h SR(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB),\ SR 60 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h SR(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB) SR 66 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h SR(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\ SR 67 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h SR(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB) SR 43 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SR(DWB_SOURCE_SELECT),\ SR 31 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A),\ SR 32 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B),\ SR 33 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C),\ SR 34 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D),\ SR 35 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A),\ SR 36 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),\ SR 37 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C),\ SR 38 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D),\ SR 39 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ SR 40 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h SR(DCHVM_CTRL0), \ SR 41 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h SR(DCHVM_MEM_CTRL), \ SR 42 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h SR(DCHVM_CLK_CTRL), \ SR 43 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h SR(DCHVM_RIOMMU_CTRL0), \ SR 44 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h SR(DCHVM_RIOMMU_STAT0) SR 50 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h SR(DCHUBBUB_CRC_CTRL), \ SR 51 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h SR(DCN_VM_FB_LOCATION_BASE),\ SR 52 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h SR(DCN_VM_FB_LOCATION_TOP),\ SR 53 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h SR(DCN_VM_FB_OFFSET),\ SR 54 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h SR(DCN_VM_AGP_BOT),\ SR 55 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h SR(DCN_VM_AGP_TOP),\ SR 56 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h SR(DCN_VM_AGP_BASE) SR 92 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h SR(DENTIST_DISPCLK_CNTL) SR 101 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h SR(DENTIST_DISPCLK_CNTL), \ SR 894 drivers/gpu/drm/i915/intel_pm.c reg |= FW_WM(wm, SR); SR 958 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->sr.plane, SR) | SR 1008 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->sr.plane, SR) | SR 2266 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(DSPFW1, FW_WM(srwm, SR) | SR 5890 drivers/gpu/drm/i915/intel_pm.c wm->sr.plane = _FW_WM(tmp, SR); SR 5930 drivers/gpu/drm/i915/intel_pm.c wm->sr.plane = _FW_WM(tmp, SR); SR 437 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, IRQENABLE); SR 438 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, CONTROL); SR 439 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, CONFIG); SR 440 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, LINE_NUMBER); SR 443 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, GLOBAL_ALPHA); SR 445 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, CONTROL2); SR 446 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, CONFIG2); SR 449 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, CONTROL3); SR 450 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, CONFIG3); SR 454 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, DEFAULT_COLOR(i)); SR 455 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, TRANS_COLOR(i)); SR 456 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, SIZE_MGR(i)); SR 459 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, TIMING_H(i)); SR 460 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, TIMING_V(i)); SR 461 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, POL_FREQ(i)); SR 462 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, DIVISORo(i)); SR 464 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, DATA_CYCLE1(i)); SR 465 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, DATA_CYCLE2(i)); SR 466 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, DATA_CYCLE3(i)); SR 469 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, CPR_COEF_R(i)); SR 470 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, CPR_COEF_G(i)); SR 471 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, CPR_COEF_B(i)); SR 476 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_BA0(i)); SR 477 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_BA1(i)); SR 478 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_POSITION(i)); SR 479 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_SIZE(i)); SR 480 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_ATTRIBUTES(i)); SR 481 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_FIFO_THRESHOLD(i)); SR 482 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_ROW_INC(i)); SR 483 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_PIXEL_INC(i)); SR 485 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_PRELOAD(i)); SR 487 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_WINDOW_SKIP(i)); SR 488 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_TABLE_BA(i)); SR 491 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_FIR(i)); SR 492 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_PICTURE_SIZE(i)); SR 493 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_ACCU0(i)); SR 494 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_ACCU1(i)); SR 497 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_FIR_COEF_H(i, j)); SR 500 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_FIR_COEF_HV(i, j)); SR 503 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_CONV_COEF(i, j)); SR 507 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_FIR_COEF_V(i, j)); SR 511 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_BA0_UV(i)); SR 512 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_BA1_UV(i)); SR 513 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_FIR2(i)); SR 514 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_ACCU2_0(i)); SR 515 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_ACCU2_1(i)); SR 518 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_FIR_COEF_H2(i, j)); SR 521 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_FIR_COEF_HV2(i, j)); SR 524 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_FIR_COEF_V2(i, j)); SR 527 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, OVL_ATTRIBUTES2(i)); SR 531 drivers/gpu/drm/omapdrm/dss/dispc.c SR(dispc, DIVISOR); SR 114 drivers/gpu/drm/omapdrm/dss/dss.c SR(dss, CONTROL); SR 117 drivers/gpu/drm/omapdrm/dss/dss.c SR(dss, SDI_CONTROL); SR 118 drivers/gpu/drm/omapdrm/dss/dss.c SR(dss, PLL_CONTROL); SR 346 drivers/macintosh/via-cuda.c (void)in_8(&via[SR]); SR 361 drivers/macintosh/via-cuda.c (void)in_8(&via[SR]); SR 389 drivers/macintosh/via-cuda.c (void)in_8(&via[SR]); /* clear any left-over data */ SR 398 drivers/macintosh/via-cuda.c (void)in_8(&via[SR]); SR 409 drivers/macintosh/via-cuda.c (void)in_8(&via[SR]); SR 418 drivers/macintosh/via-cuda.c (void)in_8(&via[SR]); SR 546 drivers/macintosh/via-cuda.c out_8(&via[SR], current_req->data[data_index++]); SR 599 drivers/macintosh/via-cuda.c (void)in_8(&via[SR]); SR 609 drivers/macintosh/via-cuda.c (void)in_8(&via[SR]); SR 620 drivers/macintosh/via-cuda.c (void)in_8(&via[SR]); SR 627 drivers/macintosh/via-cuda.c out_8(&via[SR], current_req->data[data_index++]); SR 639 drivers/macintosh/via-cuda.c (void)in_8(&via[SR]); SR 652 drivers/macintosh/via-cuda.c out_8(&via[SR], req->data[data_index++]); SR 663 drivers/macintosh/via-cuda.c (void)in_8(&via[SR]); SR 665 drivers/macintosh/via-cuda.c *reply_ptr++ = in_8(&via[SR]); SR 683 drivers/macintosh/via-cuda.c (void)in_8(&via[SR]); SR 174 drivers/macintosh/via-macii.c x = via[SR]; SR 343 drivers/macintosh/via-macii.c via[SR] = req->data[1]; SR 397 drivers/macintosh/via-macii.c x = via[SR]; SR 439 drivers/macintosh/via-macii.c x = via[SR]; SR 444 drivers/macintosh/via-macii.c via[SR] = req->data[data_index++]; SR 457 drivers/macintosh/via-macii.c x = via[SR]; SR 498 drivers/macintosh/via-macii.c x = via[SR]; SR 1215 drivers/macintosh/via-pmu.c out_8(&via1[SR], x); SR 1224 drivers/macintosh/via-pmu.c in_8(&via1[SR]); /* resets SR */ SR 1495 drivers/macintosh/via-pmu.c bite = in_8(&via1[SR]); SR 2524 drivers/macintosh/via-pmu.c via1[SR] = x; eieio(); SR 2534 drivers/macintosh/via-pmu.c x = via1[SR]; eieio(); SR 2536 drivers/macintosh/via-pmu.c x = via1[SR]; eieio(); SR 79 drivers/media/pci/ngene/ngene-core.c while (Cur->ngeneBuffer.SR.Flags & 0x80) { SR 82 drivers/media/pci/ngene/ngene-core.c if (Cur->ngeneBuffer.SR.Flags & 0x20) SR 88 drivers/media/pci/ngene/ngene-core.c Cur->ngeneBuffer.SR. SR 102 drivers/media/pci/ngene/ngene-core.c Cur->ngeneBuffer.SR.Flags &= SR 115 drivers/media/pci/ngene/ngene-core.c Cur->ngeneBuffer.SR.Flags &= ~0x40; SR 122 drivers/media/pci/ngene/ngene-core.c Cur->ngeneBuffer.SR.DTOUpdate = SR 131 drivers/media/pci/ngene/ngene-core.c if (Cur->ngeneBuffer.SR.Flags & 0x01) SR 133 drivers/media/pci/ngene/ngene-core.c if (Cur->ngeneBuffer.SR.Flags & 0x20) SR 139 drivers/media/pci/ngene/ngene-core.c Cur->ngeneBuffer.SR.Clock, SR 144 drivers/media/pci/ngene/ngene-core.c Cur->ngeneBuffer.SR.Clock, SR 150 drivers/media/pci/ngene/ngene-core.c Cur->ngeneBuffer.SR.Flags = 0x00; SR 217 drivers/media/pci/ngene/ngene-core.c ngeneBuffer.SR.Flags & 0xC0) == 0x80) { SR 219 drivers/media/pci/ngene/ngene-core.c ngeneBuffer.SR.Flags |= 0x40; SR 504 drivers/media/pci/ngene/ngene-core.c val = chan->nextBuffer->ngeneBuffer.SR.Flags & 0x80; SR 514 drivers/media/pci/ngene/ngene-core.c memset(&Cur->ngeneBuffer.SR, 0, sizeof(Cur->ngeneBuffer.SR)); SR 523 drivers/media/pci/ngene/ngene-core.c chan->nextBuffer->ngeneBuffer.SR.DTOUpdate = SR 530 drivers/media/pci/ngene/ngene-core.c memset(&Cur->ngeneBuffer.SR, 0, SR 531 drivers/media/pci/ngene/ngene-core.c sizeof(Cur->ngeneBuffer.SR)); SR 188 drivers/media/pci/ngene/ngene.h struct BUFFER_STREAM_RESULTS SR; SR 231 drivers/misc/atmel-ssc.c ssc_readl(ssc->regs, SR); SR 3362 drivers/net/ethernet/amd/xgbe/xgbe-dev.c XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1); SR 3400 drivers/net/ethernet/amd/xgbe/xgbe-dev.c XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0); SR 3449 drivers/net/ethernet/amd/xgbe/xgbe-dev.c XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1); SR 3462 drivers/net/ethernet/amd/xgbe/xgbe-dev.c XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0); SR 267 drivers/rtc/rtc-at91sam9.c sr = rtt_readl(rtc, SR) & (mr >> 16); SR 622 drivers/spi/spi-atmel.c while (spi_readl(as, SR) & SPI_BIT(RDRF)) { SR 673 drivers/spi/spi-atmel.c (void)spi_readl(as, SR); SR 1090 drivers/spi/spi-atmel.c status = spi_readl(as, SR); SR 1111 drivers/spi/spi-atmel.c spi_readl(as, SR); SR 1147 drivers/spi/spi-atmel.c status = spi_readl(as, SR); SR 1158 drivers/spi/spi-atmel.c spi_readl(as, SR); SR 1338 drivers/spi/spi-atmel.c if (spi_readl(as, SR) & SPI_BIT(TXEMPTY)) SR 1343 drivers/spi/spi-atmel.c while (spi_readl(as, SR) & SPI_BIT(RDRF)) SR 1347 drivers/spi/spi-atmel.c spi_readl(as, SR); SR 1687 drivers/spi/spi-atmel.c spi_readl(as, SR); SR 353 drivers/usb/misc/sisusbvga/sisusb_init.c SRdata = SiS_Pr->SiS_StandTable[StandTableIndex].SR[0] | 0x20; SR 357 drivers/usb/misc/sisusbvga/sisusb_init.c SRdata = SiS_Pr->SiS_StandTable[StandTableIndex].SR[i - 1]; SR 72 drivers/usb/misc/sisusbvga/sisusb_struct.h unsigned char SR[4]; SR 293 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(IRQENABLE); SR 294 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(CONTROL); SR 295 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(CONFIG); SR 296 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(LINE_NUMBER); SR 299 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(GLOBAL_ALPHA); SR 301 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(CONTROL2); SR 302 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(CONFIG2); SR 305 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(CONTROL3); SR 306 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(CONFIG3); SR 310 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(DEFAULT_COLOR(i)); SR 311 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(TRANS_COLOR(i)); SR 312 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(SIZE_MGR(i)); SR 315 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(TIMING_H(i)); SR 316 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(TIMING_V(i)); SR 317 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(POL_FREQ(i)); SR 318 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(DIVISORo(i)); SR 320 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(DATA_CYCLE1(i)); SR 321 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(DATA_CYCLE2(i)); SR 322 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(DATA_CYCLE3(i)); SR 325 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(CPR_COEF_R(i)); SR 326 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(CPR_COEF_G(i)); SR 327 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(CPR_COEF_B(i)); SR 332 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(OVL_BA0(i)); SR 333 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(OVL_BA1(i)); SR 334 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(OVL_POSITION(i)); SR 335 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(OVL_SIZE(i)); SR 336 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(OVL_ATTRIBUTES(i)); SR 337 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(OVL_FIFO_THRESHOLD(i)); SR 338 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(OVL_ROW_INC(i)); SR 339 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(OVL_PIXEL_INC(i)); SR 341 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(OVL_PRELOAD(i)); SR 343 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(OVL_WINDOW_SKIP(i)); SR 344 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(OVL_TABLE_BA(i)); SR 347 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(OVL_FIR(i)); SR 348 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(OVL_PICTURE_SIZE(i)); SR 349 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(OVL_ACCU0(i)); SR 350 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(OVL_ACCU1(i)); SR 353 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(OVL_FIR_COEF_H(i, j)); SR 356 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(OVL_FIR_COEF_HV(i, j)); SR 359 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(OVL_CONV_COEF(i, j)); SR 363 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(OVL_FIR_COEF_V(i, j)); SR 367 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(OVL_BA0_UV(i)); SR 368 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(OVL_BA1_UV(i)); SR 369 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(OVL_FIR2(i)); SR 370 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(OVL_ACCU2_0(i)); SR 371 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(OVL_ACCU2_1(i)); SR 374 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(OVL_FIR_COEF_H2(i, j)); SR 377 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(OVL_FIR_COEF_HV2(i, j)); SR 380 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(OVL_FIR_COEF_V2(i, j)); SR 383 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(OVL_ATTRIBUTES2(i)); SR 387 drivers/video/fbdev/omap2/omapfb/dss/dispc.c SR(DIVISOR); SR 132 drivers/video/fbdev/omap2/omapfb/dss/dss.c SR(CONTROL); SR 136 drivers/video/fbdev/omap2/omapfb/dss/dss.c SR(SDI_CONTROL); SR 137 drivers/video/fbdev/omap2/omapfb/dss/dss.c SR(PLL_CONTROL); SR 1840 drivers/video/fbdev/sis/init.c SRdata = SiS_Pr->SiS_StandTable[StandTableIndex].SR[0] | 0x20; SR 1854 drivers/video/fbdev/sis/init.c SRdata = SiS_Pr->SiS_StandTable[StandTableIndex].SR[i - 1]; SR 134 drivers/video/fbdev/sis/vstruct.h unsigned char SR[4]; SR 1798 drivers/video/fbdev/via/hw.c via_write_reg(VIASR, i, VPIT.SR[i - 1]); SR 15 drivers/video/fbdev/via/viamode.h unsigned char SR[StdSR]; SR 485 sound/atmel/ac97c.c u32 sr = ac97c_readl(chip, SR); SR 147 sound/soc/atmel/atmel_ssc_dai.c ssc_sr = (unsigned long)ssc_readl(ssc_p->ssc->regs, SR) SR 279 sound/soc/atmel/atmel_ssc_dai.c ssc_readl(ssc_p->ssc->regs, SR)); SR 729 sound/soc/atmel/atmel_ssc_dai.c ssc_readl(ssc_p->ssc->regs, SR)); SR 774 sound/soc/atmel/atmel_ssc_dai.c ssc_p->ssc_state.ssc_sr = ssc_readl(ssc_p->ssc->regs, SR);