SPLL_CTL 1632 drivers/gpu/drm/i915/display/intel_ddi.c pll = I915_READ(SPLL_CTL) & SPLL_FREQ_MASK; SPLL_CTL 9282 drivers/gpu/drm/i915/display/intel_display.c u32 ctl = I915_READ(SPLL_CTL); SPLL_CTL 4255 drivers/gpu/drm/i915/display/intel_display_power.c I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, SPLL_CTL 514 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(SPLL_CTL, pll->state.hw_state.spll); SPLL_CTL 515 drivers/gpu/drm/i915/display/intel_dpll_mgr.c POSTING_READ(SPLL_CTL); SPLL_CTL 543 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(SPLL_CTL); SPLL_CTL 544 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); SPLL_CTL 545 drivers/gpu/drm/i915/display/intel_dpll_mgr.c POSTING_READ(SPLL_CTL); SPLL_CTL 588 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(SPLL_CTL); SPLL_CTL 2403 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPLL_CTL, D_ALL);