SOC15_REG_OFFSET   77 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c 		SOC15_REG_OFFSET(SDMA0, 0,
SOC15_REG_OFFSET   79 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c 		SOC15_REG_OFFSET(SDMA1, 0,
SOC15_REG_OFFSET   81 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c 		SOC15_REG_OFFSET(SDMA2, 0,
SOC15_REG_OFFSET   83 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c 		SOC15_REG_OFFSET(SDMA3, 0,
SOC15_REG_OFFSET   85 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c 		SOC15_REG_OFFSET(SDMA4, 0,
SOC15_REG_OFFSET   87 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c 		SOC15_REG_OFFSET(SDMA5, 0,
SOC15_REG_OFFSET   89 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c 		SOC15_REG_OFFSET(SDMA6, 0,
SOC15_REG_OFFSET   91 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c 		SOC15_REG_OFFSET(SDMA7, 0,
SOC15_REG_OFFSET  230 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config);
SOC15_REG_OFFSET  231 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases);
SOC15_REG_OFFSET  259 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	pr_debug("ATHUB, reg %x\n", SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid);
SOC15_REG_OFFSET  260 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid,
SOC15_REG_OFFSET  265 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	while (!(RREG32(SOC15_REG_OFFSET(
SOC15_REG_OFFSET  272 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	WREG32(SOC15_REG_OFFSET(ATHUB, 0,
SOC15_REG_OFFSET  279 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid,
SOC15_REG_OFFSET  300 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL),
SOC15_REG_OFFSET  314 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 		SOC15_REG_OFFSET(SDMA0, 0,
SOC15_REG_OFFSET  322 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 		SOC15_REG_OFFSET(SDMA1, 0,
SOC15_REG_OFFSET  338 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	uint32_t retval = SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_ADDR_H) -
SOC15_REG_OFFSET  381 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 		value = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS));
SOC15_REG_OFFSET  384 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), value);
SOC15_REG_OFFSET  389 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
SOC15_REG_OFFSET  392 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	     reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
SOC15_REG_OFFSET  399 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data);
SOC15_REG_OFFSET  428 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO),
SOC15_REG_OFFSET  430 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI),
SOC15_REG_OFFSET  432 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
SOC15_REG_OFFSET  434 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
SOC15_REG_OFFSET  437 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1),
SOC15_REG_OFFSET  442 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR),
SOC15_REG_OFFSET  447 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data);
SOC15_REG_OFFSET  474 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
SOC15_REG_OFFSET  475 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	     reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
SOC15_REG_OFFSET  502 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 		SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_CONTEXT_CNTL) :
SOC15_REG_OFFSET  503 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 		SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_CONTEXT_CNTL);
SOC15_REG_OFFSET  604 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
SOC15_REG_OFFSET  609 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 		if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) &&
SOC15_REG_OFFSET  610 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 		   high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI)))
SOC15_REG_OFFSET  725 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type);
SOC15_REG_OFFSET  729 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 		temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
SOC15_REG_OFFSET  788 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
SOC15_REG_OFFSET  799 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
SOC15_REG_OFFSET  890 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), gfx_index_val);
SOC15_REG_OFFSET  891 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd);
SOC15_REG_OFFSET  900 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data);
SOC15_REG_OFFSET  929 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32) + (vmid*2), 0);
SOC15_REG_OFFSET  930 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32) + (vmid*2), 0);
SOC15_REG_OFFSET  932 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32) + (vmid*2),
SOC15_REG_OFFSET  934 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32) + (vmid*2),
SOC15_REG_OFFSET  937 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) + (vmid*2), lower_32_bits(base));
SOC15_REG_OFFSET  938 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) + (vmid*2), upper_32_bits(base));
SOC15_REG_OFFSET  141 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config);
SOC15_REG_OFFSET  142 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases);
SOC15_REG_OFFSET  169 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid,
SOC15_REG_OFFSET  172 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	while (!(RREG32(SOC15_REG_OFFSET(
SOC15_REG_OFFSET  178 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	WREG32(SOC15_REG_OFFSET(ATHUB, 0,
SOC15_REG_OFFSET  183 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid,
SOC15_REG_OFFSET  186 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID16_PASID_MAPPING) + vmid,
SOC15_REG_OFFSET  189 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	while (!(RREG32(SOC15_REG_OFFSET(
SOC15_REG_OFFSET  195 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	WREG32(SOC15_REG_OFFSET(ATHUB, 0,
SOC15_REG_OFFSET  200 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid,
SOC15_REG_OFFSET  220 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL),
SOC15_REG_OFFSET  234 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 		SOC15_REG_OFFSET(SDMA0, 0,
SOC15_REG_OFFSET  236 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 		SOC15_REG_OFFSET(SDMA1, 0,
SOC15_REG_OFFSET  282 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 		value = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS));
SOC15_REG_OFFSET  285 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 		WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), value);
SOC15_REG_OFFSET  290 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
SOC15_REG_OFFSET  293 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	     reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
SOC15_REG_OFFSET  300 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data);
SOC15_REG_OFFSET  329 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 		WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO),
SOC15_REG_OFFSET  331 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 		WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI),
SOC15_REG_OFFSET  333 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 		WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
SOC15_REG_OFFSET  335 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 		WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
SOC15_REG_OFFSET  337 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1),
SOC15_REG_OFFSET  342 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR),
SOC15_REG_OFFSET  347 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data);
SOC15_REG_OFFSET  374 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
SOC15_REG_OFFSET  375 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	     reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
SOC15_REG_OFFSET  401 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 		SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_CONTEXT_CNTL) :
SOC15_REG_OFFSET  402 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 		SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_CONTEXT_CNTL);
SOC15_REG_OFFSET  500 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
SOC15_REG_OFFSET  505 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 		if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) &&
SOC15_REG_OFFSET  506 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 		   high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI)))
SOC15_REG_OFFSET  563 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type);
SOC15_REG_OFFSET  567 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 		temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
SOC15_REG_OFFSET  626 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
SOC15_REG_OFFSET  637 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
SOC15_REG_OFFSET  758 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd);
SOC15_REG_OFFSET  396 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
SOC15_REG_OFFSET  952 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
SOC15_REG_OFFSET 1890 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
SOC15_REG_OFFSET 1893 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
SOC15_REG_OFFSET 2742 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
SOC15_REG_OFFSET 3716 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
SOC15_REG_OFFSET 3718 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
SOC15_REG_OFFSET 3724 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
SOC15_REG_OFFSET 3726 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
SOC15_REG_OFFSET 3732 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
SOC15_REG_OFFSET 3734 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
SOC15_REG_OFFSET 3740 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
SOC15_REG_OFFSET 3742 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	       (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
SOC15_REG_OFFSET 3748 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
SOC15_REG_OFFSET 3750 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	       (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
SOC15_REG_OFFSET 3756 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
SOC15_REG_OFFSET 3758 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	       (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
SOC15_REG_OFFSET 3764 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
SOC15_REG_OFFSET 3766 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	       (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
SOC15_REG_OFFSET 4001 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 				    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
SOC15_REG_OFFSET 4006 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 				    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
SOC15_REG_OFFSET 4011 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 				    SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
SOC15_REG_OFFSET 4016 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 				    SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
SOC15_REG_OFFSET 4606 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
SOC15_REG_OFFSET 4863 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 			cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
SOC15_REG_OFFSET 4866 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 			cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
SOC15_REG_OFFSET 4910 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
SOC15_REG_OFFSET 4913 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
SOC15_REG_OFFSET 4916 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
SOC15_REG_OFFSET 4919 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
SOC15_REG_OFFSET 5123 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
SOC15_REG_OFFSET 5125 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
SOC15_REG_OFFSET  801 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
SOC15_REG_OFFSET 2133 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 				   SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
SOC15_REG_OFFSET 2149 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 				   SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0);
SOC15_REG_OFFSET 2600 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
SOC15_REG_OFFSET 2602 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),
SOC15_REG_OFFSET 2604 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),
SOC15_REG_OFFSET 2675 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
SOC15_REG_OFFSET 2677 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
SOC15_REG_OFFSET 2680 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR),
SOC15_REG_OFFSET 2683 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
SOC15_REG_OFFSET 2687 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
SOC15_REG_OFFSET 2692 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
SOC15_REG_OFFSET 2720 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
SOC15_REG_OFFSET 2722 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size);
SOC15_REG_OFFSET 2725 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
SOC15_REG_OFFSET 2728 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
SOC15_REG_OFFSET 2734 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 			WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0)
SOC15_REG_OFFSET 2738 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 			WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0)
SOC15_REG_OFFSET 2759 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS));
SOC15_REG_OFFSET 2764 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 			WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
SOC15_REG_OFFSET 2770 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 			WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
SOC15_REG_OFFSET 2775 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 			WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
SOC15_REG_OFFSET 2787 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
SOC15_REG_OFFSET 2790 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
SOC15_REG_OFFSET 2798 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data);
SOC15_REG_OFFSET 2800 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2));
SOC15_REG_OFFSET 2803 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data);
SOC15_REG_OFFSET 2805 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3));
SOC15_REG_OFFSET 2808 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data);
SOC15_REG_OFFSET 2810 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL));
SOC15_REG_OFFSET 2815 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
SOC15_REG_OFFSET 2827 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
SOC15_REG_OFFSET 2832 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
SOC15_REG_OFFSET 2841 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
SOC15_REG_OFFSET 2846 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
SOC15_REG_OFFSET 2855 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
SOC15_REG_OFFSET 2860 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
SOC15_REG_OFFSET 2868 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
SOC15_REG_OFFSET 2873 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
SOC15_REG_OFFSET 2881 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
SOC15_REG_OFFSET 2886 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
SOC15_REG_OFFSET 2890 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));
SOC15_REG_OFFSET 2898 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
SOC15_REG_OFFSET 2903 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
SOC15_REG_OFFSET 2911 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
SOC15_REG_OFFSET 2916 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
SOC15_REG_OFFSET 3190 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		(SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START));
SOC15_REG_OFFSET 4106 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 				   SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
SOC15_REG_OFFSET 4111 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 				   SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
SOC15_REG_OFFSET 4116 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 				   SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
SOC15_REG_OFFSET 4121 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 				   SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
SOC15_REG_OFFSET 4319 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO)
SOC15_REG_OFFSET 4347 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO)
SOC15_REG_OFFSET 5167 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX) + pipe_num;
SOC15_REG_OFFSET 5287 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
SOC15_REG_OFFSET 5509 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
SOC15_REG_OFFSET 5512 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
SOC15_REG_OFFSET 5515 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
SOC15_REG_OFFSET 5518 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
SOC15_REG_OFFSET  363 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 		SOC15_REG_OFFSET(GC, 0,
SOC15_REG_OFFSET  366 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 		SOC15_REG_OFFSET(GC, 0,
SOC15_REG_OFFSET  369 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 		SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_SEM);
SOC15_REG_OFFSET  371 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 		SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ);
SOC15_REG_OFFSET  373 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 		SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ACK);
SOC15_REG_OFFSET  375 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 		SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL);
SOC15_REG_OFFSET  377 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 		SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
SOC15_REG_OFFSET  379 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 		SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
SOC15_REG_OFFSET  348 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 		SOC15_REG_OFFSET(GC, 0,
SOC15_REG_OFFSET  351 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 		SOC15_REG_OFFSET(GC, 0,
SOC15_REG_OFFSET  354 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 		SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_SEM);
SOC15_REG_OFFSET  356 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 		SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ);
SOC15_REG_OFFSET  358 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 		SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK);
SOC15_REG_OFFSET  360 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 		SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL);
SOC15_REG_OFFSET  362 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 		SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS);
SOC15_REG_OFFSET  364 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 		SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
SOC15_REG_OFFSET  419 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 		reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
SOC15_REG_OFFSET  421 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 		reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
SOC15_REG_OFFSET  621 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 		reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
SOC15_REG_OFFSET  623 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 		reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
SOC15_REG_OFFSET  416 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 		SOC15_REG_OFFSET(MMHUB, 0,
SOC15_REG_OFFSET  419 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 		SOC15_REG_OFFSET(MMHUB, 0,
SOC15_REG_OFFSET  422 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 		SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_SEM);
SOC15_REG_OFFSET  424 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 		SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_REQ);
SOC15_REG_OFFSET  426 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 		SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ACK);
SOC15_REG_OFFSET  428 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 		SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL);
SOC15_REG_OFFSET  430 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 		SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
SOC15_REG_OFFSET  432 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 		SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
SOC15_REG_OFFSET  339 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 		SOC15_REG_OFFSET(MMHUB, 0,
SOC15_REG_OFFSET  342 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 		SOC15_REG_OFFSET(MMHUB, 0,
SOC15_REG_OFFSET  345 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 		SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_SEM);
SOC15_REG_OFFSET  347 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 		SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_REQ);
SOC15_REG_OFFSET  349 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 		SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ACK);
SOC15_REG_OFFSET  351 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 		SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
SOC15_REG_OFFSET  353 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 		SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_STATUS);
SOC15_REG_OFFSET  355 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 		SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
SOC15_REG_OFFSET  498 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 			SOC15_REG_OFFSET(MMHUB, 0,
SOC15_REG_OFFSET  502 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 			SOC15_REG_OFFSET(MMHUB, 0,
SOC15_REG_OFFSET  506 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 			SOC15_REG_OFFSET(MMHUB, 0,
SOC15_REG_OFFSET  510 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 			SOC15_REG_OFFSET(MMHUB, 0,
SOC15_REG_OFFSET  514 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 			SOC15_REG_OFFSET(MMHUB, 0,
SOC15_REG_OFFSET  518 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 			SOC15_REG_OFFSET(MMHUB, 0,
SOC15_REG_OFFSET  522 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 			SOC15_REG_OFFSET(MMHUB, 0,
SOC15_REG_OFFSET  526 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 			SOC15_REG_OFFSET(MMHUB, 0,
SOC15_REG_OFFSET   56 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c 	return RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
SOC15_REG_OFFSET   66 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c 	reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
SOC15_REG_OFFSET  138 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c 	reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
SOC15_REG_OFFSET  142 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c 	WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0),
SOC15_REG_OFFSET  144 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c 	WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1),
SOC15_REG_OFFSET  146 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c 	WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2),
SOC15_REG_OFFSET  148 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c 	WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3),
SOC15_REG_OFFSET  187 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c                         SOC15_REG_OFFSET(NBIO, 0,
SOC15_REG_OFFSET  256 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c 				RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
SOC15_REG_OFFSET  303 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c 	u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL));
SOC15_REG_OFFSET  307 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c 	WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp);
SOC15_REG_OFFSET  356 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c 	u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL));
SOC15_REG_OFFSET  360 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c 	WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp);
SOC15_REG_OFFSET   63 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h #define AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_CONTROL) * 4
SOC15_REG_OFFSET   64 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h #define AI_MAIBOX_CONTROL_RCV_OFFSET_BYTE SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_CONTROL) * 4 + 1
SOC15_REG_OFFSET  220 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);
SOC15_REG_OFFSET  236 drivers/gpu/drm/amd/amdgpu/navi10_ih.c 	reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);
SOC15_REG_OFFSET   61 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c 		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
SOC15_REG_OFFSET   74 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c 	u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
SOC15_REG_OFFSET   75 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c 			SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
SOC15_REG_OFFSET   97 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c 	u32 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
SOC15_REG_OFFSET  251 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c 	return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_GPU_HDP_FLUSH_REQ);
SOC15_REG_OFFSET  256 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c 	return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_GPU_HDP_FLUSH_DONE);
SOC15_REG_OFFSET  261 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c 	return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
SOC15_REG_OFFSET  266 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c 	return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
SOC15_REG_OFFSET   61 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
SOC15_REG_OFFSET   73 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 	u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
SOC15_REG_OFFSET   74 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 			SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
SOC15_REG_OFFSET  211 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 	return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
SOC15_REG_OFFSET  216 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 	return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
SOC15_REG_OFFSET  221 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 	return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
SOC15_REG_OFFSET  226 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 	return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
SOC15_REG_OFFSET   80 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c 	u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
SOC15_REG_OFFSET   81 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c 			SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
SOC15_REG_OFFSET   97 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c 	u32 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
SOC15_REG_OFFSET  250 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c 	return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ);
SOC15_REG_OFFSET  255 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c 	return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE);
SOC15_REG_OFFSET  260 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c 	return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
SOC15_REG_OFFSET  265 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c 	return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
SOC15_REG_OFFSET  101 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 			SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE);
SOC15_REG_OFFSET  112 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 			SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE);
SOC15_REG_OFFSET  132 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 		reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE);
SOC15_REG_OFFSET  134 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 		reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
SOC15_REG_OFFSET  251 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 	return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ);
SOC15_REG_OFFSET  256 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 	return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE);
SOC15_REG_OFFSET  261 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 	return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
SOC15_REG_OFFSET  266 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 	return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
SOC15_REG_OFFSET   97 drivers/gpu/drm/amd/amdgpu/nv.c 	address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
SOC15_REG_OFFSET   98 drivers/gpu/drm/amd/amdgpu/nv.c 	data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
SOC15_REG_OFFSET  111 drivers/gpu/drm/amd/amdgpu/nv.c 	address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
SOC15_REG_OFFSET  112 drivers/gpu/drm/amd/amdgpu/nv.c 	data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
SOC15_REG_OFFSET  140 drivers/gpu/drm/amd/amdgpu/nv.c 	WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
SOC15_REG_OFFSET  208 drivers/gpu/drm/amd/amdgpu/nv.c 		if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
SOC15_REG_OFFSET  499 drivers/gpu/drm/amd/amdgpu/nv.c 		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
SOC15_REG_OFFSET  147 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
SOC15_REG_OFFSET  168 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
SOC15_REG_OFFSET  259 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
SOC15_REG_OFFSET  260 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c 		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
SOC15_REG_OFFSET  265 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
SOC15_REG_OFFSET  266 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c 		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
SOC15_REG_OFFSET  271 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
SOC15_REG_OFFSET  272 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c 		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
SOC15_REG_OFFSET  277 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
SOC15_REG_OFFSET  278 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c 		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
SOC15_REG_OFFSET  283 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
SOC15_REG_OFFSET  284 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c 		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
SOC15_REG_OFFSET  289 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
SOC15_REG_OFFSET  290 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c 		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
SOC15_REG_OFFSET  295 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
SOC15_REG_OFFSET  296 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c 		*sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
SOC15_REG_OFFSET  226 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
SOC15_REG_OFFSET  244 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
SOC15_REG_OFFSET  268 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
SOC15_REG_OFFSET  288 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
SOC15_REG_OFFSET  309 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
SOC15_REG_OFFSET  328 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
SOC15_REG_OFFSET  350 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 	psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
SOC15_REG_OFFSET  362 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 	psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
SOC15_REG_OFFSET  420 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
SOC15_REG_OFFSET  423 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
SOC15_REG_OFFSET  459 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
SOC15_REG_OFFSET  481 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
SOC15_REG_OFFSET  583 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
SOC15_REG_OFFSET  584 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
SOC15_REG_OFFSET  589 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
SOC15_REG_OFFSET  590 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
SOC15_REG_OFFSET  595 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
SOC15_REG_OFFSET  596 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
SOC15_REG_OFFSET  601 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
SOC15_REG_OFFSET  602 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
SOC15_REG_OFFSET  607 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
SOC15_REG_OFFSET  608 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
SOC15_REG_OFFSET  614 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 			*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
SOC15_REG_OFFSET  615 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 			*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
SOC15_REG_OFFSET  625 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 			*sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
SOC15_REG_OFFSET  626 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 			*sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
SOC15_REG_OFFSET  701 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 	offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
SOC15_REG_OFFSET  715 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 	offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
SOC15_REG_OFFSET  105 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
SOC15_REG_OFFSET  125 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
SOC15_REG_OFFSET  146 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
SOC15_REG_OFFSET  165 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
SOC15_REG_OFFSET  187 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 	psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
SOC15_REG_OFFSET  199 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 	psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
SOC15_REG_OFFSET  262 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
SOC15_REG_OFFSET  284 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
SOC15_REG_OFFSET  310 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
SOC15_REG_OFFSET  313 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
SOC15_REG_OFFSET  413 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
SOC15_REG_OFFSET  414 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
SOC15_REG_OFFSET  419 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
SOC15_REG_OFFSET  420 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
SOC15_REG_OFFSET  425 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
SOC15_REG_OFFSET  426 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
SOC15_REG_OFFSET  431 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
SOC15_REG_OFFSET  432 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
SOC15_REG_OFFSET  437 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
SOC15_REG_OFFSET  438 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
SOC15_REG_OFFSET  443 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
SOC15_REG_OFFSET  444 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
SOC15_REG_OFFSET  449 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
SOC15_REG_OFFSET  450 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 		*sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
SOC15_REG_OFFSET  521 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 	offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
SOC15_REG_OFFSET  535 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c 	offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
SOC15_REG_OFFSET  145 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
SOC15_REG_OFFSET  165 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
SOC15_REG_OFFSET  208 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
SOC15_REG_OFFSET  227 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
SOC15_REG_OFFSET  279 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 	psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
SOC15_REG_OFFSET  291 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 	psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
SOC15_REG_OFFSET  328 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0,
SOC15_REG_OFFSET  351 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0,
SOC15_REG_OFFSET  376 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 				SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
SOC15_REG_OFFSET  388 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 				SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
SOC15_REG_OFFSET  491 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
SOC15_REG_OFFSET  492 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
SOC15_REG_OFFSET  497 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
SOC15_REG_OFFSET  498 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
SOC15_REG_OFFSET  503 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
SOC15_REG_OFFSET  504 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
SOC15_REG_OFFSET  509 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
SOC15_REG_OFFSET  510 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
SOC15_REG_OFFSET  515 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
SOC15_REG_OFFSET  516 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
SOC15_REG_OFFSET  521 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
SOC15_REG_OFFSET  522 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
SOC15_REG_OFFSET  527 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 		*sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
SOC15_REG_OFFSET  528 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 		*sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
SOC15_REG_OFFSET  608 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 	offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
SOC15_REG_OFFSET  622 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 	offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
SOC15_REG_OFFSET 1162 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 		def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
SOC15_REG_OFFSET 1166 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 			WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
SOC15_REG_OFFSET 1169 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 		def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
SOC15_REG_OFFSET 1172 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 			WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
SOC15_REG_OFFSET 1181 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
SOC15_REG_OFFSET 1184 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 		WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
SOC15_REG_OFFSET 1187 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
SOC15_REG_OFFSET 1190 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 		WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
SOC15_REG_OFFSET 1193 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
SOC15_REG_OFFSET 1200 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 		WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
SOC15_REG_OFFSET 2226 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
SOC15_REG_OFFSET 2231 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
SOC15_REG_OFFSET  175 drivers/gpu/drm/amd/amdgpu/soc15.c 	address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
SOC15_REG_OFFSET  176 drivers/gpu/drm/amd/amdgpu/soc15.c 	data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
SOC15_REG_OFFSET  189 drivers/gpu/drm/amd/amdgpu/soc15.c 	address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
SOC15_REG_OFFSET  190 drivers/gpu/drm/amd/amdgpu/soc15.c 	data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
SOC15_REG_OFFSET  203 drivers/gpu/drm/amd/amdgpu/soc15.c 	address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
SOC15_REG_OFFSET  204 drivers/gpu/drm/amd/amdgpu/soc15.c 	data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
SOC15_REG_OFFSET  217 drivers/gpu/drm/amd/amdgpu/soc15.c 	address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
SOC15_REG_OFFSET  218 drivers/gpu/drm/amd/amdgpu/soc15.c 	data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
SOC15_REG_OFFSET  331 drivers/gpu/drm/amd/amdgpu/soc15.c 		rom_index_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX_VG20);
SOC15_REG_OFFSET  332 drivers/gpu/drm/amd/amdgpu/soc15.c 		rom_data_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA_VG20);
SOC15_REG_OFFSET  335 drivers/gpu/drm/amd/amdgpu/soc15.c 		rom_index_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX);
SOC15_REG_OFFSET  336 drivers/gpu/drm/amd/amdgpu/soc15.c 		rom_data_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA);
SOC15_REG_OFFSET  395 drivers/gpu/drm/amd/amdgpu/soc15.c 		if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
SOC15_REG_OFFSET  397 drivers/gpu/drm/amd/amdgpu/soc15.c 		else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
SOC15_REG_OFFSET  456 drivers/gpu/drm/amd/amdgpu/soc15.c 		if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
SOC15_REG_OFFSET  457 drivers/gpu/drm/amd/amdgpu/soc15.c 			reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
SOC15_REG_OFFSET  458 drivers/gpu/drm/amd/amdgpu/soc15.c 			reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
SOC15_REG_OFFSET  459 drivers/gpu/drm/amd/amdgpu/soc15.c 			reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
SOC15_REG_OFFSET  823 drivers/gpu/drm/amd/amdgpu/soc15.c 		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
SOC15_REG_OFFSET 1351 drivers/gpu/drm/amd/amdgpu/soc15.c 		def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
SOC15_REG_OFFSET 1365 drivers/gpu/drm/amd/amdgpu/soc15.c 			WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
SOC15_REG_OFFSET 1367 drivers/gpu/drm/amd/amdgpu/soc15.c 		def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
SOC15_REG_OFFSET 1375 drivers/gpu/drm/amd/amdgpu/soc15.c 			WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
SOC15_REG_OFFSET 1383 drivers/gpu/drm/amd/amdgpu/soc15.c 	def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
SOC15_REG_OFFSET 1405 drivers/gpu/drm/amd/amdgpu/soc15.c 		WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
SOC15_REG_OFFSET 1412 drivers/gpu/drm/amd/amdgpu/soc15.c 	def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
SOC15_REG_OFFSET 1420 drivers/gpu/drm/amd/amdgpu/soc15.c 		WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
SOC15_REG_OFFSET 1428 drivers/gpu/drm/amd/amdgpu/soc15.c 	def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
SOC15_REG_OFFSET 1438 drivers/gpu/drm/amd/amdgpu/soc15.c 		WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
SOC15_REG_OFFSET 1504 drivers/gpu/drm/amd/amdgpu/soc15.c 	data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
SOC15_REG_OFFSET 1509 drivers/gpu/drm/amd/amdgpu/soc15.c 	data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
SOC15_REG_OFFSET 1514 drivers/gpu/drm/amd/amdgpu/soc15.c 	data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
SOC15_REG_OFFSET 1519 drivers/gpu/drm/amd/amdgpu/soc15.c 	data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
SOC15_REG_OFFSET   88 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 		SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel);
SOC15_REG_OFFSET   90 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 		SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt);
SOC15_REG_OFFSET   92 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 		SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
SOC15_REG_OFFSET  134 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c                 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
SOC15_REG_OFFSET  171 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 		SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
SOC15_REG_OFFSET  220 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 		SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel);
SOC15_REG_OFFSET  222 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 		SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt);
SOC15_REG_OFFSET  550 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
SOC15_REG_OFFSET  555 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
SOC15_REG_OFFSET  560 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
SOC15_REG_OFFSET  566 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j,
SOC15_REG_OFFSET  570 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j,
SOC15_REG_OFFSET  800 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
SOC15_REG_OFFSET  804 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 				MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i,
SOC15_REG_OFFSET  807 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 				MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i,
SOC15_REG_OFFSET  810 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 				MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0);
SOC15_REG_OFFSET  813 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 				MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
SOC15_REG_OFFSET  815 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 				MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
SOC15_REG_OFFSET  818 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 				MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
SOC15_REG_OFFSET  823 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), size);
SOC15_REG_OFFSET  825 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
SOC15_REG_OFFSET  827 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
SOC15_REG_OFFSET  829 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1), (1 << 21));
SOC15_REG_OFFSET  830 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_UVD_HEAP_SIZE);
SOC15_REG_OFFSET  832 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
SOC15_REG_OFFSET  834 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
SOC15_REG_OFFSET  836 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21));
SOC15_REG_OFFSET  837 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2),
SOC15_REG_OFFSET  840 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_GP_SCRATCH4), adev->uvd.max_handles);
SOC15_REG_OFFSET  844 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_CGC_CTRL),
SOC15_REG_OFFSET  848 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),
SOC15_REG_OFFSET  852 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),
SOC15_REG_OFFSET  857 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET),
SOC15_REG_OFFSET  868 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL),
SOC15_REG_OFFSET  877 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET),
SOC15_REG_OFFSET  881 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),
SOC15_REG_OFFSET  885 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),
SOC15_REG_OFFSET  890 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
SOC15_REG_OFFSET  897 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp);
SOC15_REG_OFFSET  901 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), ring->gpu_addr);
SOC15_REG_OFFSET  902 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr));
SOC15_REG_OFFSET  903 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), ring->ring_size / 4);
SOC15_REG_OFFSET  906 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 0);
SOC15_REG_OFFSET  909 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),
SOC15_REG_OFFSET  912 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0x02, 0x02);
SOC15_REG_OFFSET  942 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_POWER_STATUS), 0,
SOC15_REG_OFFSET  957 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0,
SOC15_REG_OFFSET  961 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 0,
SOC15_REG_OFFSET  965 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2),
SOC15_REG_OFFSET 1016 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 0,
SOC15_REG_OFFSET 1037 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET),
SOC15_REG_OFFSET 1041 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 			WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 0,
SOC15_REG_OFFSET 1052 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN),
SOC15_REG_OFFSET 1057 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0,
SOC15_REG_OFFSET 1090 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_RBC_RB_CNTL), 0,
SOC15_REG_OFFSET 1128 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),
SOC15_REG_OFFSET 1142 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0,
SOC15_REG_OFFSET 1163 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));
SOC15_REG_OFFSET 1166 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
SOC15_REG_OFFSET 1169 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
SOC15_REG_OFFSET 1172 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
SOC15_REG_OFFSET 1176 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
SOC15_REG_OFFSET 1179 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
SOC15_REG_OFFSET 1182 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
SOC15_REG_OFFSET 1237 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));
SOC15_REG_OFFSET 1299 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_VMID), 0));
SOC15_REG_OFFSET 1303 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
SOC15_REG_OFFSET 1306 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));
SOC15_REG_OFFSET 1309 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_RBC_IB_SIZE), 0));
SOC15_REG_OFFSET 1341 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
SOC15_REG_OFFSET 1344 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
SOC15_REG_OFFSET 1347 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
SOC15_REG_OFFSET 1357 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
SOC15_REG_OFFSET 1360 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
SOC15_REG_OFFSET 1363 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GP_SCRATCH8), 0));
SOC15_REG_OFFSET 1366 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
SOC15_REG_OFFSET 1393 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_NO_OP), 0));
SOC15_REG_OFFSET   66 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR));
SOC15_REG_OFFSET   68 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2));
SOC15_REG_OFFSET   70 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR3));
SOC15_REG_OFFSET   88 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR));
SOC15_REG_OFFSET   90 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2));
SOC15_REG_OFFSET   92 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3));
SOC15_REG_OFFSET  114 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR),
SOC15_REG_OFFSET  117 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2),
SOC15_REG_OFFSET  120 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3),
SOC15_REG_OFFSET  131 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 				RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS));
SOC15_REG_OFFSET  139 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET),
SOC15_REG_OFFSET  143 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), 0,
SOC15_REG_OFFSET  163 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO), lower_32_bits(addr));
SOC15_REG_OFFSET  164 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI), upper_32_bits(addr));
SOC15_REG_OFFSET  167 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_VMID));
SOC15_REG_OFFSET  170 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_VMID), data);
SOC15_REG_OFFSET  173 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_SIZE), size);
SOC15_REG_OFFSET  176 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP), 0);
SOC15_REG_OFFSET  184 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST), 0x10000001);
SOC15_REG_OFFSET  186 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP));
SOC15_REG_OFFSET  190 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP));
SOC15_REG_OFFSET  233 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO),
SOC15_REG_OFFSET  235 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI),
SOC15_REG_OFFSET  237 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_SIZE),
SOC15_REG_OFFSET  241 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL), 0x398000);
SOC15_REG_OFFSET  242 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CACHE_CTRL), ~0x1, 0);
SOC15_REG_OFFSET  243 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL), 0);
SOC15_REG_OFFSET  244 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL1), 0);
SOC15_REG_OFFSET  245 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VM_CTRL), 0);
SOC15_REG_OFFSET  253 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
SOC15_REG_OFFSET  255 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
SOC15_REG_OFFSET  258 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0), 0);
SOC15_REG_OFFSET  260 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
SOC15_REG_OFFSET  263 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
SOC15_REG_OFFSET  266 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0),
SOC15_REG_OFFSET  270 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
SOC15_REG_OFFSET  273 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
SOC15_REG_OFFSET  276 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
SOC15_REG_OFFSET  279 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
SOC15_REG_OFFSET  284 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE0), size);
SOC15_REG_OFFSET  288 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET1),
SOC15_REG_OFFSET  290 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE1), size);
SOC15_REG_OFFSET  294 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET2),
SOC15_REG_OFFSET  296 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE2), size);
SOC15_REG_OFFSET  298 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL2), ~0x100, 0);
SOC15_REG_OFFSET  299 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN),
SOC15_REG_OFFSET  304 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS),
SOC15_REG_OFFSET  306 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL),
SOC15_REG_OFFSET  308 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET),
SOC15_REG_OFFSET  311 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS),
SOC15_REG_OFFSET  316 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS),
SOC15_REG_OFFSET  342 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR), lower_32_bits(ring->wptr));
SOC15_REG_OFFSET  343 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR), lower_32_bits(ring->wptr));
SOC15_REG_OFFSET  344 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO), ring->gpu_addr);
SOC15_REG_OFFSET  345 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI), upper_32_bits(ring->gpu_addr));
SOC15_REG_OFFSET  346 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_SIZE), ring->ring_size / 4);
SOC15_REG_OFFSET  350 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2), lower_32_bits(ring->wptr));
SOC15_REG_OFFSET  351 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2), lower_32_bits(ring->wptr));
SOC15_REG_OFFSET  352 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO2), ring->gpu_addr);
SOC15_REG_OFFSET  353 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI2), upper_32_bits(ring->gpu_addr));
SOC15_REG_OFFSET  354 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_SIZE2), ring->ring_size / 4);
SOC15_REG_OFFSET  358 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR3), lower_32_bits(ring->wptr));
SOC15_REG_OFFSET  359 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3), lower_32_bits(ring->wptr));
SOC15_REG_OFFSET  360 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO3), ring->gpu_addr);
SOC15_REG_OFFSET  361 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI3), upper_32_bits(ring->gpu_addr));
SOC15_REG_OFFSET  362 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_SIZE3), ring->ring_size / 4);
SOC15_REG_OFFSET  365 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), VCE_STATUS__JOB_BUSY_MASK,
SOC15_REG_OFFSET  368 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL), 1, ~0x200001);
SOC15_REG_OFFSET  370 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), 0,
SOC15_REG_OFFSET  377 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), 0, ~VCE_STATUS__JOB_BUSY_MASK);
SOC15_REG_OFFSET  391 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL), 0, ~0x200001);
SOC15_REG_OFFSET  394 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET),
SOC15_REG_OFFSET  399 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), 0);
SOC15_REG_OFFSET  607 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_A), 0, ~(1 << 16));
SOC15_REG_OFFSET  608 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING), 0x1FF000, ~0xFF9FF000);
SOC15_REG_OFFSET  609 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING), 0x3F, ~0x3F);
SOC15_REG_OFFSET  610 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B), 0x1FF);
SOC15_REG_OFFSET  612 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL), 0x00398000);
SOC15_REG_OFFSET  613 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CACHE_CTRL), 0x0, ~0x1);
SOC15_REG_OFFSET  614 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL), 0);
SOC15_REG_OFFSET  615 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL1), 0);
SOC15_REG_OFFSET  616 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VM_CTRL), 0);
SOC15_REG_OFFSET  623 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),
SOC15_REG_OFFSET  625 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR0),
SOC15_REG_OFFSET  627 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0), 0);
SOC15_REG_OFFSET  629 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),
SOC15_REG_OFFSET  631 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR0),
SOC15_REG_OFFSET  633 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0), offset & ~0x0f000000);
SOC15_REG_OFFSET  637 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE0), size);
SOC15_REG_OFFSET  639 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR1), (adev->vce.gpu_addr >> 8));
SOC15_REG_OFFSET  640 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR1), (adev->vce.gpu_addr >> 40) & 0xff);
SOC15_REG_OFFSET  643 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET1), (offset & ~0x0f000000) | (1 << 24));
SOC15_REG_OFFSET  644 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE1), size);
SOC15_REG_OFFSET  646 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR2), (adev->vce.gpu_addr >> 8));
SOC15_REG_OFFSET  647 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR2), (adev->vce.gpu_addr >> 40) & 0xff);
SOC15_REG_OFFSET  650 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET2), (offset & ~0x0f000000) | (2 << 24));
SOC15_REG_OFFSET  651 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE2), size);
SOC15_REG_OFFSET  653 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL2), 0x0, ~0x100);
SOC15_REG_OFFSET  654 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN),
SOC15_REG_OFFSET  716 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	if (RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {
SOC15_REG_OFFSET  721 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	if (RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {
SOC15_REG_OFFSET  797 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 	tmp = data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_ARB_CTRL));
SOC15_REG_OFFSET  804 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_ARB_CTRL), data);
SOC15_REG_OFFSET  821 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B));
SOC15_REG_OFFSET  824 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B), data);
SOC15_REG_OFFSET  826 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING));
SOC15_REG_OFFSET  829 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING), data);
SOC15_REG_OFFSET  831 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING_2));
SOC15_REG_OFFSET  834 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING_2), data);
SOC15_REG_OFFSET  836 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING));
SOC15_REG_OFFSET  838 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING), data);
SOC15_REG_OFFSET  840 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_DMA_DCLK_CTRL));
SOC15_REG_OFFSET  845 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_DMA_DCLK_CTRL), data);
SOC15_REG_OFFSET  847 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B));
SOC15_REG_OFFSET  850 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B), data);
SOC15_REG_OFFSET  852 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING));
SOC15_REG_OFFSET  854 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING), data);
SOC15_REG_OFFSET  856 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING_2));
SOC15_REG_OFFSET  858 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING_2), data);
SOC15_REG_OFFSET  860 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING));
SOC15_REG_OFFSET  862 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING), data);
SOC15_REG_OFFSET  864 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_DMA_DCLK_CTRL));
SOC15_REG_OFFSET  869 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_DMA_DCLK_CTRL), data);
SOC15_REG_OFFSET  911 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 			uint32_t data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_A);
SOC15_REG_OFFSET  914 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 			WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_A, data);
SOC15_REG_OFFSET  917 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 			data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING);
SOC15_REG_OFFSET  920 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 			WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING, data);
SOC15_REG_OFFSET 1020 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 		WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN), val,
SOC15_REG_OFFSET  134 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
SOC15_REG_OFFSET  136 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
SOC15_REG_OFFSET  138 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
SOC15_REG_OFFSET  140 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
SOC15_REG_OFFSET  142 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
SOC15_REG_OFFSET  160 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH);
SOC15_REG_OFFSET  801 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
SOC15_REG_OFFSET  850 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
SOC15_REG_OFFSET  854 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
SOC15_REG_OFFSET  876 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
SOC15_REG_OFFSET  880 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
SOC15_REG_OFFSET  891 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
SOC15_REG_OFFSET  895 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN),
SOC15_REG_OFFSET  934 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
SOC15_REG_OFFSET 1107 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
SOC15_REG_OFFSET 1152 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
SOC15_REG_OFFSET 1161 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
SOC15_REG_OFFSET 1165 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
SOC15_REG_OFFSET 1169 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
SOC15_REG_OFFSET 1208 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
SOC15_REG_OFFSET 1446 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
SOC15_REG_OFFSET 1449 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
SOC15_REG_OFFSET 1465 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
SOC15_REG_OFFSET 1485 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
SOC15_REG_OFFSET 1488 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
SOC15_REG_OFFSET 1491 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
SOC15_REG_OFFSET 1494 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
SOC15_REG_OFFSET 1498 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
SOC15_REG_OFFSET 1501 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
SOC15_REG_OFFSET 1504 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
SOC15_REG_OFFSET 1525 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));
SOC15_REG_OFFSET 1529 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
SOC15_REG_OFFSET 1532 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));
SOC15_REG_OFFSET 1535 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0));
SOC15_REG_OFFSET 1546 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
SOC15_REG_OFFSET 1549 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
SOC15_REG_OFFSET 1552 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0));
SOC15_REG_OFFSET 1555 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
SOC15_REG_OFFSET 1580 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
SOC15_REG_OFFSET 1583 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
SOC15_REG_OFFSET 1586 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
SOC15_REG_OFFSET 1775 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
SOC15_REG_OFFSET 1794 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
SOC15_REG_OFFSET 1817 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_DATA0), 0, 0, PACKETJ_TYPE0));
SOC15_REG_OFFSET 1821 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_DATA1), 0, 0, PACKETJ_TYPE0));
SOC15_REG_OFFSET 1825 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
SOC15_REG_OFFSET 1829 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
SOC15_REG_OFFSET 1833 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_CMD), 0, 0, PACKETJ_TYPE0));
SOC15_REG_OFFSET 1837 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_CMD), 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));
SOC15_REG_OFFSET 1841 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
SOC15_REG_OFFSET 1845 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
SOC15_REG_OFFSET 1849 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
SOC15_REG_OFFSET 1853 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
SOC15_REG_OFFSET 1861 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
SOC15_REG_OFFSET 1890 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_VMID), 0, 0, PACKETJ_TYPE0));
SOC15_REG_OFFSET 1894 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JPEG_VMID), 0, 0, PACKETJ_TYPE0));
SOC15_REG_OFFSET 1898 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
SOC15_REG_OFFSET 1902 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
SOC15_REG_OFFSET 1906 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_IB_SIZE), 0, 0, PACKETJ_TYPE0));
SOC15_REG_OFFSET 1910 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
SOC15_REG_OFFSET 1914 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
SOC15_REG_OFFSET 1922 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
SOC15_REG_OFFSET 1926 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
SOC15_REG_OFFSET 1930 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_STATUS), 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3));
SOC15_REG_OFFSET 1942 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
SOC15_REG_OFFSET 1946 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
SOC15_REG_OFFSET 1950 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
SOC15_REG_OFFSET 1986 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
SOC15_REG_OFFSET 2015 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	ring->ring[(*ptr)++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0);
SOC15_REG_OFFSET 2034 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW);
SOC15_REG_OFFSET 2040 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH);
SOC15_REG_OFFSET 2052 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
SOC15_REG_OFFSET 2058 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA);
SOC15_REG_OFFSET 2064 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
SOC15_REG_OFFSET 2069 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0);
SOC15_REG_OFFSET 2071 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0);
SOC15_REG_OFFSET 2073 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0);
SOC15_REG_OFFSET 2091 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_RPTR);
SOC15_REG_OFFSET 2097 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 	reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
SOC15_REG_OFFSET 2147 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 		amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0));
SOC15_REG_OFFSET  177 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	adev->vcn.inst->external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
SOC15_REG_OFFSET  179 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
SOC15_REG_OFFSET  181 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
SOC15_REG_OFFSET  183 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	adev->vcn.inst->external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
SOC15_REG_OFFSET  185 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	adev->vcn.inst->external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
SOC15_REG_OFFSET  208 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	adev->vcn.inst->external.jpeg_pitch = SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH);
SOC15_REG_OFFSET  674 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_PGFSM_CONFIG), tmp);
SOC15_REG_OFFSET  686 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS)) & ~0x1;
SOC15_REG_OFFSET  687 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS), tmp);
SOC15_REG_OFFSET  705 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_JMI_CNTL), 0,
SOC15_REG_OFFSET  709 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32_P(SOC15_REG_OFFSET(VCN, 0, mmJPEG_SYS_INT_EN),
SOC15_REG_OFFSET  741 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_JMI_CNTL),
SOC15_REG_OFFSET  762 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS));
SOC15_REG_OFFSET  765 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS), tmp);
SOC15_REG_OFFSET  768 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_PGFSM_CONFIG), tmp);
SOC15_REG_OFFSET 1081 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
SOC15_REG_OFFSET 1085 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
SOC15_REG_OFFSET 1125 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
SOC15_REG_OFFSET 1129 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
SOC15_REG_OFFSET 1159 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 		WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
SOC15_REG_OFFSET 1163 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 		WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
SOC15_REG_OFFSET 1175 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
SOC15_REG_OFFSET 1180 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
SOC15_REG_OFFSET 1253 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
SOC15_REG_OFFSET 1300 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
SOC15_REG_OFFSET 1304 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
SOC15_REG_OFFSET 1309 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
SOC15_REG_OFFSET 1314 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
SOC15_REG_OFFSET  176 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		adev->vcn.inst[j].external.scratch9 = SOC15_REG_OFFSET(UVD, j, mmUVD_SCRATCH9);
SOC15_REG_OFFSET  178 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(UVD, j, mmUVD_GPCOM_VCPU_DATA0);
SOC15_REG_OFFSET  180 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(UVD, j, mmUVD_GPCOM_VCPU_DATA1);
SOC15_REG_OFFSET  182 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(UVD, j, mmUVD_GPCOM_VCPU_CMD);
SOC15_REG_OFFSET  184 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(UVD, j, mmUVD_NO_OP);
SOC15_REG_OFFSET  187 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		adev->vcn.inst[j].external.jpeg_pitch = SOC15_REG_OFFSET(UVD, j, mmUVD_JPEG_PITCH);
SOC15_REG_OFFSET  620 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JPEG_POWER_STATUS), 0,
SOC15_REG_OFFSET  651 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JMI_CNTL), 0,
SOC15_REG_OFFSET  655 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmJPEG_SYS_INT_EN),
SOC15_REG_OFFSET  691 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JMI_CNTL),
SOC15_REG_OFFSET  703 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JPEG_POWER_STATUS),
SOC15_REG_OFFSET  721 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_POWER_STATUS), 0,
SOC15_REG_OFFSET  736 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),
SOC15_REG_OFFSET  740 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), 0,
SOC15_REG_OFFSET  791 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0,
SOC15_REG_OFFSET  795 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_ARB_CTRL), 0,
SOC15_REG_OFFSET  798 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 0,
SOC15_REG_OFFSET  818 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 			WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),
SOC15_REG_OFFSET  822 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 			WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 0,
SOC15_REG_OFFSET  835 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),
SOC15_REG_OFFSET  840 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0,
SOC15_REG_OFFSET  923 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_ARB_CTRL),
SOC15_REG_OFFSET  928 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),
SOC15_REG_OFFSET  933 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 0,
SOC15_REG_OFFSET  942 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_POWER_STATUS),
SOC15_REG_OFFSET  386 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);
SOC15_REG_OFFSET  388 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1);
SOC15_REG_OFFSET  390 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2);
SOC15_REG_OFFSET  411 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);
SOC15_REG_OFFSET  413 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1);
SOC15_REG_OFFSET  415 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2);
SOC15_REG_OFFSET  484 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR);
SOC15_REG_OFFSET  486 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1);
SOC15_REG_OFFSET  488 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2);
SOC15_REG_OFFSET   54 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
SOC15_REG_OFFSET   64 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c 	reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
SOC15_REG_OFFSET   73 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);