SM_INC             25 arch/sh/drivers/dma/dma-sh.c #define RS_DUAL	(DM_INC | SM_INC | RS_AUTO | TS_INDEX2VAL(XMIT_SZ_32BIT))
SM_INC             30 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
SM_INC             40 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
SM_INC             50 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
SM_INC             60 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
SM_INC             70 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
SM_INC             80 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT),
SM_INC             36 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
SM_INC             46 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
SM_INC             56 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
SM_INC             66 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
SM_INC             76 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
SM_INC             86 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
SM_INC             96 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
SM_INC            106 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
SM_INC            116 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
SM_INC            126 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
SM_INC            136 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT),
SM_INC            146 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 		.chcr		= DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT),
SM_INC            120 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= SM_INC | RS_ERS | 0x40000000 |
SM_INC            134 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= SM_INC | RS_ERS | 0x40000000 |
SM_INC            151 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= SM_INC | RS_ERS | 0x40000000 |
SM_INC            165 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= SM_INC | RS_ERS | 0x40000000 |
SM_INC            179 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= SM_INC | RS_ERS | 0x40000000 |
SM_INC            193 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= SM_INC | RS_ERS | 0x40000000 |
SM_INC            210 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= SM_INC | RS_ERS | 0x40000000 |
SM_INC            224 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= SM_INC | RS_ERS | 0x40000000 |
SM_INC            238 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= SM_INC | RS_ERS | 0x40000000 |
SM_INC            252 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= SM_INC | RS_ERS | 0x40000000 |
SM_INC            266 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= SM_INC | RS_ERS | 0x40000000 |
SM_INC            283 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= SM_INC | RS_ERS | 0x40000000 |
SM_INC            297 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= SM_INC | RS_ERS | 0x40000000 |
SM_INC            311 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= SM_INC | RS_ERS | 0x40000000 |
SM_INC            325 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= SM_INC | RS_ERS | 0x40000000 |
SM_INC            339 arch/sh/kernel/cpu/sh4a/setup-sh7757.c 		.chcr		= SM_INC | RS_ERS | 0x40000000 |
SM_INC             45 drivers/dma/sh/shdma-arm.h #define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL((xmit_sz)))
SM_INC            239 drivers/dma/sh/shdmac.c 	u32 chcr = DM_INC | SM_INC | RS_AUTO | log2size_to_chcr(sh_chan,