SMU__NUM_MCLK_DPM_LEVELS   42 drivers/gpu/drm/amd/powerplay/inc/smu7.h #define SMU7_MAX_LEVELS_MEMORY          SMU__NUM_MCLK_DPM_LEVELS   // MCLK Levels DPM
SMU__NUM_MCLK_DPM_LEVELS   62 drivers/gpu/drm/amd/powerplay/inc/smu71.h #define SMU71_MAX_LEVELS_MEMORY          SMU__NUM_MCLK_DPM_LEVELS
SMU__NUM_MCLK_DPM_LEVELS  179 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h     SMU71_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
SMU__NUM_MCLK_DPM_LEVELS  110 drivers/gpu/drm/amd/powerplay/inc/smu72.h #define SMU72_MAX_LEVELS_MEMORY          SMU__NUM_MCLK_DPM_LEVELS   /* MCLK Levels DPM */
SMU__NUM_MCLK_DPM_LEVELS  166 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h 	SMU72_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
SMU__NUM_MCLK_DPM_LEVELS  109 drivers/gpu/drm/amd/powerplay/inc/smu73.h #define SMU73_MAX_LEVELS_MEMORY          SMU__NUM_MCLK_DPM_LEVELS   // MCLK Levels DPM
SMU__NUM_MCLK_DPM_LEVELS  156 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h     SMU73_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
SMU__NUM_MCLK_DPM_LEVELS  135 drivers/gpu/drm/amd/powerplay/inc/smu74.h #define SMU74_MAX_LEVELS_MEMORY          SMU__NUM_MCLK_DPM_LEVELS   /* MCLK Levels DPM */
SMU__NUM_MCLK_DPM_LEVELS  179 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h 	SMU74_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
SMU__NUM_MCLK_DPM_LEVELS   56 drivers/gpu/drm/amd/powerplay/inc/smu75.h #define SMU75_MAX_LEVELS_MEMORY          SMU__NUM_MCLK_DPM_LEVELS
SMU__NUM_MCLK_DPM_LEVELS  192 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h 	SMU75_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
SMU__NUM_MCLK_DPM_LEVELS  235 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h     SMU7_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
SMU__NUM_MCLK_DPM_LEVELS   42 drivers/gpu/drm/radeon/smu7.h #define SMU7_MAX_LEVELS_MEMORY          SMU__NUM_MCLK_DPM_LEVELS   // MCLK Levels DPM
SMU__NUM_MCLK_DPM_LEVELS  235 drivers/gpu/drm/radeon/smu7_discrete.h     SMU7_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];