SMU_SCLK_DPM_STATE_0_CNTL_0  597 drivers/gpu/drm/radeon/trinity_dpm.c 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
SMU_SCLK_DPM_STATE_0_CNTL_0  600 drivers/gpu/drm/radeon/trinity_dpm.c 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);
SMU_SCLK_DPM_STATE_0_CNTL_0  644 drivers/gpu/drm/radeon/trinity_dpm.c 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
SMU_SCLK_DPM_STATE_0_CNTL_0  647 drivers/gpu/drm/radeon/trinity_dpm.c 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);
SMU_SCLK_DPM_STATE_0_CNTL_0  649 drivers/gpu/drm/radeon/trinity_dpm.c 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
SMU_SCLK_DPM_STATE_0_CNTL_0  652 drivers/gpu/drm/radeon/trinity_dpm.c 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);
SMU_SCLK_DPM_STATE_0_CNTL_0  740 drivers/gpu/drm/radeon/trinity_dpm.c 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
SMU_SCLK_DPM_STATE_0_CNTL_0  744 drivers/gpu/drm/radeon/trinity_dpm.c 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);
SMU_SCLK_DPM_STATE_0_CNTL_0   28 drivers/gpu/drm/radeon/trinity_dpm.h #define TRINITY_SIZEOF_DPM_STATE_TABLE (SMU_SCLK_DPM_STATE_1_CNTL_0 - SMU_SCLK_DPM_STATE_0_CNTL_0)