SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE  420 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h     uint32_t value[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE  429 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h     SMU7_Discrete_MCRegisterAddress     address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE 1730 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			PP_ASSERT_WITH_CODE(i < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE,
SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE 2556 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	PP_ASSERT_WITH_CODE((table->last <= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE 2588 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		PP_ASSERT_WITH_CODE((j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE 2604 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			PP_ASSERT_WITH_CODE((j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE 2620 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				PP_ASSERT_WITH_CODE((j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE   50 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.h 	uint32_t mc_data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE   58 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.h 	SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE 4344 drivers/gpu/drm/radeon/ci_dpm.c 		if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE 4356 drivers/gpu/drm/radeon/ci_dpm.c 			if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE 4369 drivers/gpu/drm/radeon/ci_dpm.c 			if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE 4380 drivers/gpu/drm/radeon/ci_dpm.c 				if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE 4393 drivers/gpu/drm/radeon/ci_dpm.c 			if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE 4512 drivers/gpu/drm/radeon/ci_dpm.c 	if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE 4548 drivers/gpu/drm/radeon/ci_dpm.c 			if (table->last >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE 4691 drivers/gpu/drm/radeon/ci_dpm.c 			if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE   79 drivers/gpu/drm/radeon/ci_dpm.h 	u32 mc_data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE   87 drivers/gpu/drm/radeon/ci_dpm.h 	SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE  419 drivers/gpu/drm/radeon/smu7_discrete.h     uint32_t value[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE  428 drivers/gpu/drm/radeon/smu7_discrete.h     SMU7_Discrete_MCRegisterAddress     address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];