SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE 364 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h uint32_t value[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE]; SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE 372 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h SMU72_Discrete_MCRegisterAddress address[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE]; SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE 2073 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c i < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE, SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE 2948 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE((table->last <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE 2980 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE 2997 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE 3013 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE 51 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.h uint32_t mc_data[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE]; SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE 59 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.h SMU72_Discrete_MCRegisterAddress mc_reg_address[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE];