SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE  360 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h     uint32_t value[SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE];
SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE  369 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h     SMU71_Discrete_MCRegisterAddress     address[SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE];
SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE 1697 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 			PP_ASSERT_WITH_CODE(i < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE,
SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE 2485 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	PP_ASSERT_WITH_CODE((table->last <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE 2517 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE 2533 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 			PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE 2550 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 				PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE   49 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.h 	uint32_t mc_data[SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE];
SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE   57 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.h 	SMU71_Discrete_MCRegisterAddress mc_reg_address[SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE];