SMMU_PMCG_CNTENCLR0  177 drivers/perf/arm_smmuv3_pmu.c 	writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_CNTENCLR0);
SMMU_PMCG_CNTENCLR0  704 drivers/perf/arm_smmuv3_pmu.c 		       smmu_pmu->reg_base + SMMU_PMCG_CNTENCLR0);