SMI               211 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_NOOP,                          SMI,    F,  1,      S  ),
SMI               212 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_USER_INTERRUPT,                SMI,    F,  1,      R  ),
SMI               213 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_WAIT_FOR_EVENT,                SMI,    F,  1,      R  ),
SMI               214 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_ARB_CHECK,                     SMI,    F,  1,      S  ),
SMI               215 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_REPORT_HEAD,                   SMI,    F,  1,      S  ),
SMI               216 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_SUSPEND_FLUSH,                 SMI,    F,  1,      S  ),
SMI               217 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_SEMAPHORE_MBOX,                SMI,   !F,  0xFF,   R  ),
SMI               218 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_STORE_DWORD_INDEX,             SMI,   !F,  0xFF,   R  ),
SMI               219 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_LOAD_REGISTER_IMM(1),          SMI,   !F,  0xFF,   W,
SMI               221 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_STORE_REGISTER_MEM,            SMI,    F,  3,     W | B,
SMI               228 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_LOAD_REGISTER_MEM,             SMI,    F,  3,     W | B,
SMI               240 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_BATCH_BUFFER_START,            SMI,   !F,  0xFF,   S  ),
SMI               244 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_FLUSH,                         SMI,    F,  1,      S  ),
SMI               245 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_ARB_ON_OFF,                    SMI,    F,  1,      R  ),
SMI               246 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_PREDICATE,                     SMI,    F,  1,      S  ),
SMI               247 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_TOPOLOGY_FILTER,               SMI,    F,  1,      S  ),
SMI               248 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_SET_APPID,                     SMI,    F,  1,      S  ),
SMI               249 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_DISPLAY_FLIP,                  SMI,   !F,  0xFF,   R  ),
SMI               250 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_SET_CONTEXT,                   SMI,   !F,  0xFF,   R  ),
SMI               251 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_URB_CLEAR,                     SMI,   !F,  0xFF,   S  ),
SMI               252 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0x3F,   B,
SMI               258 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0xFF,   R  ),
SMI               259 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_CLFLUSH,                       SMI,   !F,  0x3FF,  B,
SMI               265 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_REPORT_PERF_COUNT,             SMI,   !F,  0x3F,   B,
SMI               271 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_CONDITIONAL_BATCH_BUFFER_END,  SMI,   !F,  0xFF,   B,
SMI               305 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_SET_PREDICATE,                 SMI,    F,  1,      S  ),
SMI               306 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_RS_CONTROL,                    SMI,    F,  1,      S  ),
SMI               307 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_URB_ATOMIC_ALLOC,              SMI,    F,  1,      S  ),
SMI               308 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_SET_APPID,                     SMI,    F,  1,      S  ),
SMI               309 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_RS_CONTEXT,                    SMI,    F,  1,      S  ),
SMI               310 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_LOAD_SCAN_LINES_INCL,          SMI,   !F,  0x3F,   R  ),
SMI               311 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_LOAD_SCAN_LINES_EXCL,          SMI,   !F,  0x3F,   R  ),
SMI               312 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_LOAD_REGISTER_REG,             SMI,   !F,  0xFF,   W,
SMI               314 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_RS_STORE_DATA_IMM,             SMI,   !F,  0xFF,   S  ),
SMI               315 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_LOAD_URB_MEM,                  SMI,   !F,  0xFF,   S  ),
SMI               316 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_STORE_URB_MEM,                 SMI,   !F,  0xFF,   S  ),
SMI               328 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_ARB_ON_OFF,                    SMI,    F,  1,      R  ),
SMI               329 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_SET_APPID,                     SMI,    F,  1,      S  ),
SMI               330 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0xFF,   B,
SMI               336 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0x3F,   R  ),
SMI               337 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_FLUSH_DW,                      SMI,   !F,  0x3F,   B,
SMI               357 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_CONDITIONAL_BATCH_BUFFER_END,  SMI,   !F,  0xFF,   B,
SMI               372 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_ARB_ON_OFF,                    SMI,    F,  1,      R  ),
SMI               373 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_SET_APPID,                     SMI,    F,  1,      S  ),
SMI               374 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0xFF,   B,
SMI               380 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0x3F,   R  ),
SMI               381 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_FLUSH_DW,                      SMI,   !F,  0x3F,   B,
SMI               401 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_CONDITIONAL_BATCH_BUFFER_END,  SMI,   !F,  0xFF,   B,
SMI               410 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_DISPLAY_FLIP,                  SMI,   !F,  0xFF,   R  ),
SMI               411 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0x3FF,  B,
SMI               417 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0x3F,   R  ),
SMI               418 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_FLUSH_DW,                      SMI,   !F,  0x3F,   B,
SMI               443 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_LOAD_SCAN_LINES_INCL,          SMI,   !F,  0x3F,   R  ),
SMI               444 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_LOAD_SCAN_LINES_EXCL,          SMI,   !F,  0x3F,   R  ),
SMI               465 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_NOOP,                          SMI,    F,  1,      S  ),
SMI               466 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_USER_INTERRUPT,                SMI,    F,  1,      S  ),
SMI               467 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_WAIT_FOR_EVENT,                SMI,    F,  1,      S  ),
SMI               468 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_FLUSH,                         SMI,    F,  1,      S  ),
SMI               469 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_ARB_CHECK,                     SMI,    F,  1,      S  ),
SMI               470 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_REPORT_HEAD,                   SMI,    F,  1,      S  ),
SMI               471 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_ARB_ON_OFF,                    SMI,    F,  1,      S  ),
SMI               472 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_SUSPEND_FLUSH,                 SMI,    F,  1,      S  ),
SMI               473 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_LOAD_SCAN_LINES_INCL,          SMI,   !F,  0x3F,   S  ),
SMI               474 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_LOAD_SCAN_LINES_EXCL,          SMI,   !F,  0x3F,   S  ),
SMI               475 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0x3FF,  S  ),
SMI               476 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_LOAD_REGISTER_IMM(1),          SMI,   !F,  0xFF,   W,
SMI               478 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0x3FF,  S  ),
SMI               479 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_STORE_REGISTER_MEM_GEN8,       SMI,    F,  4,      W,
SMI               481 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_FLUSH_DW,                      SMI,   !F,  0x3F,   S  ),
SMI               482 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_LOAD_REGISTER_MEM_GEN8,        SMI,    F,  4,      W,
SMI               484 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_LOAD_REGISTER_REG,             SMI,    !F,  0xFF,  W,
SMI               491 drivers/gpu/drm/i915/i915_cmd_parser.c #define MI_BB_START_OPERAND_MASK   GENMASK(SMI-1, 0)
SMI               493 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(  MI_BATCH_BUFFER_START_GEN8,       SMI,    !F,  0xFF,  B,
SMI               502 drivers/gpu/drm/i915/i915_cmd_parser.c 	CMD(MI_NOOP, SMI, F, 1, S);
SMI               566 drivers/net/ethernet/amd/xgbe/xgbe-drv.c 		if (XGMAC_GET_BITS(mac_isr, MAC_ISR, SMI)) {
SMI              1293 drivers/net/ethernet/marvell/pxa168_eth.c 	for (i = 0; rdl(pep, SMI) & SMI_BUSY; i++) {
SMI              1312 drivers/net/ethernet/marvell/pxa168_eth.c 	wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) | SMI_OP_R);
SMI              1314 drivers/net/ethernet/marvell/pxa168_eth.c 	for (i = 0; !((val = rdl(pep, SMI)) & SMI_R_VALID); i++) {
SMI              1336 drivers/net/ethernet/marvell/pxa168_eth.c 	wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) |