SMEMC_VIRT 15 arch/arm/mach-pxa/include/mach/smemc.h #define MDCNFG (SMEMC_VIRT + 0x00) /* SDRAM Configuration Register 0 */ SMEMC_VIRT 16 arch/arm/mach-pxa/include/mach/smemc.h #define MDREFR (SMEMC_VIRT + 0x04) /* SDRAM Refresh Control Register */ SMEMC_VIRT 17 arch/arm/mach-pxa/include/mach/smemc.h #define MSC0 (SMEMC_VIRT + 0x08) /* Static Memory Control Register 0 */ SMEMC_VIRT 18 arch/arm/mach-pxa/include/mach/smemc.h #define MSC1 (SMEMC_VIRT + 0x0C) /* Static Memory Control Register 1 */ SMEMC_VIRT 19 arch/arm/mach-pxa/include/mach/smemc.h #define MSC2 (SMEMC_VIRT + 0x10) /* Static Memory Control Register 2 */ SMEMC_VIRT 20 arch/arm/mach-pxa/include/mach/smemc.h #define MECR (SMEMC_VIRT + 0x14) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ SMEMC_VIRT 21 arch/arm/mach-pxa/include/mach/smemc.h #define SXLCR (SMEMC_VIRT + 0x18) /* LCR value to be written to SDRAM-Timing Synchronous Flash */ SMEMC_VIRT 22 arch/arm/mach-pxa/include/mach/smemc.h #define SXCNFG (SMEMC_VIRT + 0x1C) /* Synchronous Static Memory Control Register */ SMEMC_VIRT 23 arch/arm/mach-pxa/include/mach/smemc.h #define SXMRS (SMEMC_VIRT + 0x24) /* MRS value to be written to Synchronous Flash or SMROM */ SMEMC_VIRT 24 arch/arm/mach-pxa/include/mach/smemc.h #define MCMEM0 (SMEMC_VIRT + 0x28) /* Card interface Common Memory Space Socket 0 Timing */ SMEMC_VIRT 25 arch/arm/mach-pxa/include/mach/smemc.h #define MCMEM1 (SMEMC_VIRT + 0x2C) /* Card interface Common Memory Space Socket 1 Timing */ SMEMC_VIRT 26 arch/arm/mach-pxa/include/mach/smemc.h #define MCATT0 (SMEMC_VIRT + 0x30) /* Card interface Attribute Space Socket 0 Timing Configuration */ SMEMC_VIRT 27 arch/arm/mach-pxa/include/mach/smemc.h #define MCATT1 (SMEMC_VIRT + 0x34) /* Card interface Attribute Space Socket 1 Timing Configuration */ SMEMC_VIRT 28 arch/arm/mach-pxa/include/mach/smemc.h #define MCIO0 (SMEMC_VIRT + 0x38) /* Card interface I/O Space Socket 0 Timing Configuration */ SMEMC_VIRT 29 arch/arm/mach-pxa/include/mach/smemc.h #define MCIO1 (SMEMC_VIRT + 0x3C) /* Card interface I/O Space Socket 1 Timing Configuration */ SMEMC_VIRT 30 arch/arm/mach-pxa/include/mach/smemc.h #define MDMRS (SMEMC_VIRT + 0x40) /* MRS value to be written to SDRAM */ SMEMC_VIRT 31 arch/arm/mach-pxa/include/mach/smemc.h #define BOOT_DEF (SMEMC_VIRT + 0x44) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */ SMEMC_VIRT 32 arch/arm/mach-pxa/include/mach/smemc.h #define MEMCLKCFG (SMEMC_VIRT + 0x68) /* Clock Configuration */ SMEMC_VIRT 33 arch/arm/mach-pxa/include/mach/smemc.h #define CSADRCFG0 (SMEMC_VIRT + 0x80) /* Address Configuration Register for CS0 */ SMEMC_VIRT 34 arch/arm/mach-pxa/include/mach/smemc.h #define CSADRCFG1 (SMEMC_VIRT + 0x84) /* Address Configuration Register for CS1 */ SMEMC_VIRT 35 arch/arm/mach-pxa/include/mach/smemc.h #define CSADRCFG2 (SMEMC_VIRT + 0x88) /* Address Configuration Register for CS2 */ SMEMC_VIRT 36 arch/arm/mach-pxa/include/mach/smemc.h #define CSADRCFG3 (SMEMC_VIRT + 0x8C) /* Address Configuration Register for CS3 */ SMEMC_VIRT 37 arch/arm/mach-pxa/include/mach/smemc.h #define CSMSADRCFG (SMEMC_VIRT + 0xA0) /* Chip Select Configuration Register */ SMEMC_VIRT 44 arch/arm/mach-pxa/include/mach/smemc.h #define MCMEM(s) (SMEMC_VIRT + 0x28 + ((s)<<2)) /* Card interface Common Memory Space Socket s Timing */ SMEMC_VIRT 45 arch/arm/mach-pxa/include/mach/smemc.h #define MCATT(s) (SMEMC_VIRT + 0x30 + ((s)<<2)) /* Card interface Attribute Space Socket s Timing Configuration */ SMEMC_VIRT 46 arch/arm/mach-pxa/include/mach/smemc.h #define MCIO(s) (SMEMC_VIRT + 0x38 + ((s)<<2)) /* Card interface I/O Space Socket s Timing Configuration */ SMEMC_VIRT 167 arch/arm/mach-pxa/pxa25x.c .virtual = (unsigned long)SMEMC_VIRT, SMEMC_VIRT 249 arch/arm/mach-pxa/pxa27x.c .virtual = (unsigned long)SMEMC_VIRT, SMEMC_VIRT 374 arch/arm/mach-pxa/pxa3xx.c .virtual = (unsigned long)SMEMC_VIRT,