SMC_SYSCON_RESET_CNTL  113 drivers/gpu/drm/amd/amdgpu/si_smc.c 	u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
SMC_SYSCON_RESET_CNTL  117 drivers/gpu/drm/amd/amdgpu/si_smc.c 	WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
SMC_SYSCON_RESET_CNTL  129 drivers/gpu/drm/amd/amdgpu/si_smc.c 	tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL) |
SMC_SYSCON_RESET_CNTL  131 drivers/gpu/drm/amd/amdgpu/si_smc.c 	WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
SMC_SYSCON_RESET_CNTL  155 drivers/gpu/drm/amd/amdgpu/si_smc.c 	u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
SMC_SYSCON_RESET_CNTL 1901 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 0);
SMC_SYSCON_RESET_CNTL 2361 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 1);
SMC_SYSCON_RESET_CNTL  108 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			SMC_SYSCON_RESET_CNTL, rst_reg, 1);
SMC_SYSCON_RESET_CNTL  123 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			SMC_SYSCON_RESET_CNTL, rst_reg, 0);
SMC_SYSCON_RESET_CNTL  176 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			SMC_SYSCON_RESET_CNTL, rst_reg, 1);
SMC_SYSCON_RESET_CNTL  191 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			SMC_SYSCON_RESET_CNTL, rst_reg, 0);
SMC_SYSCON_RESET_CNTL  112 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 				  SMC_SYSCON_RESET_CNTL, rst_reg, 0);
SMC_SYSCON_RESET_CNTL  120 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 				  SMC_SYSCON_RESET_CNTL,
SMC_SYSCON_RESET_CNTL  208 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 					SMC_SYSCON_RESET_CNTL, rst_reg, 1);
SMC_SYSCON_RESET_CNTL  222 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 					SMC_SYSCON_RESET_CNTL, rst_reg, 0);
SMC_SYSCON_RESET_CNTL  243 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 					SMC_SYSCON_RESET_CNTL, rst_reg, 1);
SMC_SYSCON_RESET_CNTL  246 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 					SMC_SYSCON_RESET_CNTL, rst_reg, 0);
SMC_SYSCON_RESET_CNTL  267 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 					SMC_SYSCON_RESET_CNTL,
SMC_SYSCON_RESET_CNTL  281 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 					SMC_SYSCON_RESET_CNTL, rst_reg, 0);
SMC_SYSCON_RESET_CNTL  103 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		SMC_SYSCON_RESET_CNTL, rst_reg, 1);
SMC_SYSCON_RESET_CNTL  119 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		SMC_SYSCON_RESET_CNTL, rst_reg, 0);
SMC_SYSCON_RESET_CNTL  169 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		SMC_SYSCON_RESET_CNTL, rst_reg, 1);
SMC_SYSCON_RESET_CNTL  185 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		SMC_SYSCON_RESET_CNTL, rst_reg, 0);
SMC_SYSCON_RESET_CNTL  109 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 					SMC_SYSCON_RESET_CNTL, rst_reg, 1);
SMC_SYSCON_RESET_CNTL  123 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 					SMC_SYSCON_RESET_CNTL, rst_reg, 0);
SMC_SYSCON_RESET_CNTL  144 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 					SMC_SYSCON_RESET_CNTL, rst_reg, 1);
SMC_SYSCON_RESET_CNTL  147 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 					SMC_SYSCON_RESET_CNTL, rst_reg, 0);
SMC_SYSCON_RESET_CNTL  168 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 					SMC_SYSCON_RESET_CNTL,
SMC_SYSCON_RESET_CNTL  182 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 					SMC_SYSCON_RESET_CNTL, rst_reg, 0);
SMC_SYSCON_RESET_CNTL  116 drivers/gpu/drm/radeon/ci_smc.c 	u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
SMC_SYSCON_RESET_CNTL  119 drivers/gpu/drm/radeon/ci_smc.c 	WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
SMC_SYSCON_RESET_CNTL  124 drivers/gpu/drm/radeon/ci_smc.c 	u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
SMC_SYSCON_RESET_CNTL  127 drivers/gpu/drm/radeon/ci_smc.c 	WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
SMC_SYSCON_RESET_CNTL  115 drivers/gpu/drm/radeon/si_smc.c 	u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
SMC_SYSCON_RESET_CNTL  119 drivers/gpu/drm/radeon/si_smc.c 	WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
SMC_SYSCON_RESET_CNTL  131 drivers/gpu/drm/radeon/si_smc.c 	tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
SMC_SYSCON_RESET_CNTL  133 drivers/gpu/drm/radeon/si_smc.c 	WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
SMC_SYSCON_RESET_CNTL  163 drivers/gpu/drm/radeon/si_smc.c 	u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL);