SMC_SYSCON_CLOCK_CNTL_0 1807 drivers/gpu/drm/amd/amdgpu/cik.c 	if ((0 == REG_GET_FIELD(clock_cntl, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) &&
SMC_SYSCON_CLOCK_CNTL_0  143 drivers/gpu/drm/amd/amdgpu/si_smc.c 	u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
SMC_SYSCON_CLOCK_CNTL_0  150 drivers/gpu/drm/amd/amdgpu/si_smc.c 	WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
SMC_SYSCON_CLOCK_CNTL_0  156 drivers/gpu/drm/amd/amdgpu/si_smc.c 	u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
SMC_SYSCON_CLOCK_CNTL_0  194 drivers/gpu/drm/amd/amdgpu/si_smc.c 		tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
SMC_SYSCON_CLOCK_CNTL_0 1019 drivers/gpu/drm/amd/amdgpu/vi.c 	if ((0 == REG_GET_FIELD(clock_cntl, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) &&
SMC_SYSCON_CLOCK_CNTL_0  189 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable))
SMC_SYSCON_CLOCK_CNTL_0 1899 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
SMC_SYSCON_CLOCK_CNTL_0 2360 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 1);
SMC_SYSCON_CLOCK_CNTL_0  119 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
SMC_SYSCON_CLOCK_CNTL_0  187 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
SMC_SYSCON_CLOCK_CNTL_0  128 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 				  SMC_SYSCON_CLOCK_CNTL_0,
SMC_SYSCON_CLOCK_CNTL_0  135 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 				  SMC_SYSCON_CLOCK_CNTL_0,
SMC_SYSCON_CLOCK_CNTL_0  218 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 					SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
SMC_SYSCON_CLOCK_CNTL_0  278 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 					SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
SMC_SYSCON_CLOCK_CNTL_0  162 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	return ((0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable))
SMC_SYSCON_CLOCK_CNTL_0  115 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
SMC_SYSCON_CLOCK_CNTL_0  181 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
SMC_SYSCON_CLOCK_CNTL_0  119 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 					SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
SMC_SYSCON_CLOCK_CNTL_0  179 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 					SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
SMC_SYSCON_CLOCK_CNTL_0  139 drivers/gpu/drm/radeon/ci_smc.c 	u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
SMC_SYSCON_CLOCK_CNTL_0  143 drivers/gpu/drm/radeon/ci_smc.c 	WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
SMC_SYSCON_CLOCK_CNTL_0  148 drivers/gpu/drm/radeon/ci_smc.c 	u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
SMC_SYSCON_CLOCK_CNTL_0  152 drivers/gpu/drm/radeon/ci_smc.c 	WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
SMC_SYSCON_CLOCK_CNTL_0  157 drivers/gpu/drm/radeon/ci_smc.c 	u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
SMC_SYSCON_CLOCK_CNTL_0  176 drivers/gpu/drm/radeon/ci_smc.c 		tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
SMC_SYSCON_CLOCK_CNTL_0  145 drivers/gpu/drm/radeon/si_smc.c 	u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
SMC_SYSCON_CLOCK_CNTL_0  149 drivers/gpu/drm/radeon/si_smc.c 	WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
SMC_SYSCON_CLOCK_CNTL_0  154 drivers/gpu/drm/radeon/si_smc.c 	u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
SMC_SYSCON_CLOCK_CNTL_0  158 drivers/gpu/drm/radeon/si_smc.c 	WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
SMC_SYSCON_CLOCK_CNTL_0  164 drivers/gpu/drm/radeon/si_smc.c 	u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
SMC_SYSCON_CLOCK_CNTL_0  202 drivers/gpu/drm/radeon/si_smc.c 		tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);