SMC_NIslands_MCRegisterAddress 317 drivers/gpu/drm/amd/amdgpu/si_dpm.h typedef struct SMC_NIslands_MCRegisterAddress SMC_NIslands_MCRegisterAddress; SMC_NIslands_MCRegisterAddress 323 drivers/gpu/drm/amd/amdgpu/si_dpm.h SMC_NIslands_MCRegisterAddress address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; SMC_NIslands_MCRegisterAddress 625 drivers/gpu/drm/amd/amdgpu/si_dpm.h SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; SMC_NIslands_MCRegisterAddress 933 drivers/gpu/drm/amd/amdgpu/si_dpm.h SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE]; SMC_NIslands_MCRegisterAddress 57 drivers/gpu/drm/radeon/ni_dpm.h SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; SMC_NIslands_MCRegisterAddress 258 drivers/gpu/drm/radeon/nislands_smc.h typedef struct SMC_NIslands_MCRegisterAddress SMC_NIslands_MCRegisterAddress; SMC_NIslands_MCRegisterAddress 272 drivers/gpu/drm/radeon/nislands_smc.h SMC_NIslands_MCRegisterAddress address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; SMC_NIslands_MCRegisterAddress 117 drivers/gpu/drm/radeon/si_dpm.h SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];