SMC_NIslands_MCArbDramTimingRegisterSet 1617 drivers/gpu/drm/radeon/ni_dpm.c 						SMC_NIslands_MCArbDramTimingRegisterSet *arb_regs)
SMC_NIslands_MCArbDramTimingRegisterSet 1644 drivers/gpu/drm/radeon/ni_dpm.c 	SMC_NIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
SMC_NIslands_MCArbDramTimingRegisterSet 1655 drivers/gpu/drm/radeon/ni_dpm.c 						    sizeof(SMC_NIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i)),
SMC_NIslands_MCArbDramTimingRegisterSet 1657 drivers/gpu/drm/radeon/ni_dpm.c 					      (u16)sizeof(SMC_NIslands_MCArbDramTimingRegisterSet),
SMC_NIslands_MCArbDramTimingRegisterSet  286 drivers/gpu/drm/radeon/nislands_smc.h typedef struct SMC_NIslands_MCArbDramTimingRegisterSet SMC_NIslands_MCArbDramTimingRegisterSet;
SMC_NIslands_MCArbDramTimingRegisterSet  292 drivers/gpu/drm/radeon/nislands_smc.h     SMC_NIslands_MCArbDramTimingRegisterSet     data[20];