SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE  301 drivers/gpu/drm/amd/amdgpu/si_dpm.h     uint32_t value[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE];
SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE  308 drivers/gpu/drm/amd/amdgpu/si_dpm.h 	u32 mc_data[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE];
SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE  323 drivers/gpu/drm/amd/amdgpu/si_dpm.h     SMC_NIslands_MCRegisterAddress      address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE];
SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE  625 drivers/gpu/drm/amd/amdgpu/si_dpm.h 	SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE];
SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE 2719 drivers/gpu/drm/radeon/ni_dpm.c 			if (j >= SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)
SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE 2729 drivers/gpu/drm/radeon/ni_dpm.c 			if (j >= SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)
SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE 2743 drivers/gpu/drm/radeon/ni_dpm.c 			if (j > SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)
SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE 2755 drivers/gpu/drm/radeon/ni_dpm.c 			if (j > SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)
SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE 2850 drivers/gpu/drm/radeon/ni_dpm.c 	if (table->last > SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)
SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE 2930 drivers/gpu/drm/radeon/ni_dpm.c 			if (i >= SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)
SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE   49 drivers/gpu/drm/radeon/ni_dpm.h 	u32 mc_data[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE];
SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE   57 drivers/gpu/drm/radeon/ni_dpm.h 	SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE];
SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE  263 drivers/gpu/drm/radeon/nislands_smc.h     uint32_t value[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE];
SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE  272 drivers/gpu/drm/radeon/nislands_smc.h     SMC_NIslands_MCRegisterAddress      address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE];