SIRFSOC_CLKC_ROOT_CLK_EN0_SET 1057 drivers/clk/sirf/clk-atlas7.c 	{ 0, "audmscm_kas", "kas_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 0, 0, 0, &root0_gate_lock },
SIRFSOC_CLKC_ROOT_CLK_EN0_SET 1058 drivers/clk/sirf/clk-atlas7.c 	{ 1, "gnssm_gnss", "gnss_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 1, 0, 0, &root0_gate_lock },
SIRFSOC_CLKC_ROOT_CLK_EN0_SET 1059 drivers/clk/sirf/clk-atlas7.c 	{ 2, "gpum_gpu", "gpu_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 2, 0, 0, &root0_gate_lock },
SIRFSOC_CLKC_ROOT_CLK_EN0_SET 1060 drivers/clk/sirf/clk-atlas7.c 	{ 3, "mediam_g2d", "g2d_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 3, 0, 0, &root0_gate_lock },
SIRFSOC_CLKC_ROOT_CLK_EN0_SET 1061 drivers/clk/sirf/clk-atlas7.c 	{ 4, "mediam_jpenc", "jpenc_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 4, 0, 0, &root0_gate_lock },
SIRFSOC_CLKC_ROOT_CLK_EN0_SET 1062 drivers/clk/sirf/clk-atlas7.c 	{ 5, "vdifm_disp0", "disp0_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 5, 0, 0, &root0_gate_lock },
SIRFSOC_CLKC_ROOT_CLK_EN0_SET 1063 drivers/clk/sirf/clk-atlas7.c 	{ 6, "vdifm_disp1", "disp1_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 6, 0, 0, &root0_gate_lock },
SIRFSOC_CLKC_ROOT_CLK_EN0_SET 1064 drivers/clk/sirf/clk-atlas7.c 	{ 7, "audmscm_i2s", "i2s_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 8, 0, 0, &root0_gate_lock },
SIRFSOC_CLKC_ROOT_CLK_EN0_SET 1065 drivers/clk/sirf/clk-atlas7.c 	{ 8, "audmscm_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 11, 0, 0, &root0_gate_lock },
SIRFSOC_CLKC_ROOT_CLK_EN0_SET 1066 drivers/clk/sirf/clk-atlas7.c 	{ 9, "vdifm_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 12, 0, 0, &root0_gate_lock },
SIRFSOC_CLKC_ROOT_CLK_EN0_SET 1067 drivers/clk/sirf/clk-atlas7.c 	{ 10, "gnssm_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 13, 0, 0, &root0_gate_lock },
SIRFSOC_CLKC_ROOT_CLK_EN0_SET 1068 drivers/clk/sirf/clk-atlas7.c 	{ 11, "mediam_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 14, 0, 0, &root0_gate_lock },
SIRFSOC_CLKC_ROOT_CLK_EN0_SET 1069 drivers/clk/sirf/clk-atlas7.c 	{ 12, "btm_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 17, 0, 0, &root0_gate_lock },
SIRFSOC_CLKC_ROOT_CLK_EN0_SET 1070 drivers/clk/sirf/clk-atlas7.c 	{ 13, "mediam_sdphy01", "sdphy01_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 18, 0, 0, &root0_gate_lock },
SIRFSOC_CLKC_ROOT_CLK_EN0_SET 1071 drivers/clk/sirf/clk-atlas7.c 	{ 14, "vdifm_sdphy23", "sdphy23_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 19, 0, 0, &root0_gate_lock },
SIRFSOC_CLKC_ROOT_CLK_EN0_SET 1072 drivers/clk/sirf/clk-atlas7.c 	{ 15, "vdifm_sdphy45", "sdphy45_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 20, 0, 0, &root0_gate_lock },
SIRFSOC_CLKC_ROOT_CLK_EN0_SET 1073 drivers/clk/sirf/clk-atlas7.c 	{ 16, "vdifm_sdphy67", "sdphy67_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 21, 0, 0, &root0_gate_lock },
SIRFSOC_CLKC_ROOT_CLK_EN0_SET 1074 drivers/clk/sirf/clk-atlas7.c 	{ 17, "audmscm_xin", "xin", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 22, 0, 0, &root0_gate_lock },
SIRFSOC_CLKC_ROOT_CLK_EN0_SET 1075 drivers/clk/sirf/clk-atlas7.c 	{ 18, "mediam_nand", "nand_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 27, 0, 0, &root0_gate_lock },
SIRFSOC_CLKC_ROOT_CLK_EN0_SET 1076 drivers/clk/sirf/clk-atlas7.c 	{ 19, "gnssm_sec", "sec_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 28, 0, 0, &root0_gate_lock },
SIRFSOC_CLKC_ROOT_CLK_EN0_SET 1077 drivers/clk/sirf/clk-atlas7.c 	{ 20, "cpum_cpu", "cpu_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 29, 0, 0, &root0_gate_lock },
SIRFSOC_CLKC_ROOT_CLK_EN0_SET 1078 drivers/clk/sirf/clk-atlas7.c 	{ 21, "gnssm_xin", "xin", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 30, 0, 0, &root0_gate_lock },
SIRFSOC_CLKC_ROOT_CLK_EN0_SET 1079 drivers/clk/sirf/clk-atlas7.c 	{ 22, "vdifm_vip", "vip_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 31, 0, 0, &root0_gate_lock },
SIRFSOC_CLKC_ROOT_CLK_EN0_SET 1208 drivers/clk/sirf/clk-atlas7.c 	reg = clk->regofs + SIRFSOC_CLKC_ROOT_CLK_EN0_STAT - SIRFSOC_CLKC_ROOT_CLK_EN0_SET;
SIRFSOC_CLKC_ROOT_CLK_EN0_SET 1239 drivers/clk/sirf/clk-atlas7.c 	reg = clk->regofs + SIRFSOC_CLKC_ROOT_CLK_EN0_CLR - SIRFSOC_CLKC_ROOT_CLK_EN0_SET;