SIMM 44 arch/mips/mm/uasm-micromips.c [insn_addiu] = {M(mm_addiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM}, SIMM 54 arch/mips/mm/uasm-micromips.c [insn_cache] = {M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT | RS | SIMM}, SIMM 80 arch/mips/mm/uasm-micromips.c [insn_lb] = {M(mm_lb32_op, 0, 0, 0, 0, 0), RT | RS | SIMM}, SIMM 82 arch/mips/mm/uasm-micromips.c [insn_lh] = {M(mm_lh32_op, 0, 0, 0, 0, 0), RT | RS | SIMM}, SIMM 83 arch/mips/mm/uasm-micromips.c [insn_ll] = {M(mm_pool32c_op, 0, 0, (mm_ll_func << 1), 0, 0), RS | RT | SIMM}, SIMM 85 arch/mips/mm/uasm-micromips.c [insn_lui] = {M(mm_pool32i_op, mm_lui_op, 0, 0, 0, 0), RS | SIMM}, SIMM 86 arch/mips/mm/uasm-micromips.c [insn_lw] = {M(mm_lw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM}, SIMM 96 arch/mips/mm/uasm-micromips.c [insn_pref] = {M(mm_pool32c_op, 0, 0, (mm_pref_func << 1), 0, 0), RT | RS | SIMM}, SIMM 98 arch/mips/mm/uasm-micromips.c [insn_sc] = {M(mm_pool32c_op, 0, 0, (mm_sc_func << 1), 0, 0), RT | RS | SIMM}, SIMM 104 arch/mips/mm/uasm-micromips.c [insn_sltiu] = {M(mm_sltiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM}, SIMM 112 arch/mips/mm/uasm-micromips.c [insn_sw] = {M(mm_sw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM}, SIMM 189 arch/mips/mm/uasm-micromips.c if (ip->fields & SIMM) SIMM 51 arch/mips/mm/uasm-mips.c [insn_addiu] = {M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, SIMM 68 arch/mips/mm/uasm-mips.c [insn_cache] = {M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, SIMM 76 arch/mips/mm/uasm-mips.c [insn_daddiu] = {M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, SIMM 120 arch/mips/mm/uasm-mips.c [insn_lb] = {M(lb_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, SIMM 121 arch/mips/mm/uasm-mips.c [insn_lbu] = {M(lbu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, SIMM 122 arch/mips/mm/uasm-mips.c [insn_ld] = {M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, SIMM 126 arch/mips/mm/uasm-mips.c [insn_lh] = {M(lh_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, SIMM 127 arch/mips/mm/uasm-mips.c [insn_lhu] = {M(lhu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, SIMM 129 arch/mips/mm/uasm-mips.c [insn_ll] = {M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, SIMM 130 arch/mips/mm/uasm-mips.c [insn_lld] = {M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, SIMM 135 arch/mips/mm/uasm-mips.c [insn_lui] = {M(lui_op, 0, 0, 0, 0, 0), RT | SIMM}, SIMM 136 arch/mips/mm/uasm-mips.c [insn_lw] = {M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, SIMM 137 arch/mips/mm/uasm-mips.c [insn_lwu] = {M(lwu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, SIMM 163 arch/mips/mm/uasm-mips.c [insn_pref] = {M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, SIMM 169 arch/mips/mm/uasm-mips.c [insn_sb] = {M(sb_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, SIMM 171 arch/mips/mm/uasm-mips.c [insn_sc] = {M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, SIMM 172 arch/mips/mm/uasm-mips.c [insn_scd] = {M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, SIMM 177 arch/mips/mm/uasm-mips.c [insn_sd] = {M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, SIMM 180 arch/mips/mm/uasm-mips.c [insn_sh] = {M(sh_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, SIMM 184 arch/mips/mm/uasm-mips.c [insn_slti] = {M(slti_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, SIMM 185 arch/mips/mm/uasm-mips.c [insn_sltiu] = {M(sltiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, SIMM 192 arch/mips/mm/uasm-mips.c [insn_sw] = {M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, SIMM 253 arch/mips/mm/uasm-mips.c if (ip->fields & SIMM) SIMM 747 arch/powerpc/xmon/ppc-opc.c #define TE SIMM SIMM 751 arch/powerpc/xmon/ppc-opc.c #define UIMM SIMM + 1 SIMM 3304 arch/powerpc/xmon/ppc-opc.c {"evsplati", VX (4, 553), VX_MASK, PPCSPE, 0, {RS, SIMM}}, SIMM 3306 arch/powerpc/xmon/ppc-opc.c {"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, 0, {RS, SIMM}}, SIMM 3441 arch/powerpc/xmon/ppc-opc.c {"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC, 0, {VD, SIMM}}, SIMM 3483 arch/powerpc/xmon/ppc-opc.c {"vspltish", VX (4, 844), VXVB_MASK, PPCVEC, 0, {VD, SIMM}}, SIMM 3499 arch/powerpc/xmon/ppc-opc.c {"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},