SH_CLK_MSTP32     126 arch/sh/kernel/cpu/sh4a/clock-sh7343.c   SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
SH_CLK_MSTP32     129 arch/sh/kernel/cpu/sh4a/clock-sh7366.c   SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
SH_CLK_MSTP32     142 arch/sh/kernel/cpu/sh4a/clock-sh7722.c 	[HWBLK_URAM]  = SH_CLK_MSTP32(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
SH_CLK_MSTP32     143 arch/sh/kernel/cpu/sh4a/clock-sh7722.c 	[HWBLK_XYMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
SH_CLK_MSTP32     144 arch/sh/kernel/cpu/sh4a/clock-sh7722.c 	[HWBLK_TMU]   = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
SH_CLK_MSTP32     145 arch/sh/kernel/cpu/sh4a/clock-sh7722.c 	[HWBLK_CMT]   = SH_CLK_MSTP32(&r_clk,		  MSTPCR0, 14, 0),
SH_CLK_MSTP32     146 arch/sh/kernel/cpu/sh4a/clock-sh7722.c 	[HWBLK_RWDT]  = SH_CLK_MSTP32(&r_clk,		  MSTPCR0, 13, 0),
SH_CLK_MSTP32     147 arch/sh/kernel/cpu/sh4a/clock-sh7722.c 	[HWBLK_FLCTL] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
SH_CLK_MSTP32     148 arch/sh/kernel/cpu/sh4a/clock-sh7722.c 	[HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
SH_CLK_MSTP32     149 arch/sh/kernel/cpu/sh4a/clock-sh7722.c 	[HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
SH_CLK_MSTP32     150 arch/sh/kernel/cpu/sh4a/clock-sh7722.c 	[HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
SH_CLK_MSTP32     152 arch/sh/kernel/cpu/sh4a/clock-sh7722.c 	[HWBLK_IIC]   = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
SH_CLK_MSTP32     153 arch/sh/kernel/cpu/sh4a/clock-sh7722.c 	[HWBLK_RTC]   = SH_CLK_MSTP32(&r_clk,		  MSTPCR1, 8, 0),
SH_CLK_MSTP32     155 arch/sh/kernel/cpu/sh4a/clock-sh7722.c 	[HWBLK_SDHI]  = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
SH_CLK_MSTP32     156 arch/sh/kernel/cpu/sh4a/clock-sh7722.c 	[HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk,		  MSTPCR2, 14, 0),
SH_CLK_MSTP32     157 arch/sh/kernel/cpu/sh4a/clock-sh7722.c 	[HWBLK_USBF]  = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
SH_CLK_MSTP32     158 arch/sh/kernel/cpu/sh4a/clock-sh7722.c 	[HWBLK_2DG]   = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 9, 0),
SH_CLK_MSTP32     159 arch/sh/kernel/cpu/sh4a/clock-sh7722.c 	[HWBLK_SIU]   = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 8, 0),
SH_CLK_MSTP32     160 arch/sh/kernel/cpu/sh4a/clock-sh7722.c 	[HWBLK_JPU]   = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0),
SH_CLK_MSTP32     161 arch/sh/kernel/cpu/sh4a/clock-sh7722.c 	[HWBLK_VOU]   = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
SH_CLK_MSTP32     162 arch/sh/kernel/cpu/sh4a/clock-sh7722.c 	[HWBLK_BEU]   = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
SH_CLK_MSTP32     163 arch/sh/kernel/cpu/sh4a/clock-sh7722.c 	[HWBLK_CEU]   = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
SH_CLK_MSTP32     164 arch/sh/kernel/cpu/sh4a/clock-sh7722.c 	[HWBLK_VEU]   = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0),
SH_CLK_MSTP32     165 arch/sh/kernel/cpu/sh4a/clock-sh7722.c 	[HWBLK_VPU]   = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0),
SH_CLK_MSTP32     166 arch/sh/kernel/cpu/sh4a/clock-sh7722.c 	[HWBLK_LCDC]  = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 0, 0),
SH_CLK_MSTP32     143 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_TLB]    = SH_CLK_MSTP32(&div4_clks[DIV4_I],  MSTPCR0, 31, CLK_ENABLE_ON_INIT),
SH_CLK_MSTP32     144 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_IC]     = SH_CLK_MSTP32(&div4_clks[DIV4_I],  MSTPCR0, 30, CLK_ENABLE_ON_INIT),
SH_CLK_MSTP32     145 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_OC]     = SH_CLK_MSTP32(&div4_clks[DIV4_I],  MSTPCR0, 29, CLK_ENABLE_ON_INIT),
SH_CLK_MSTP32     146 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_L2C]    = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
SH_CLK_MSTP32     147 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_ILMEM]  = SH_CLK_MSTP32(&div4_clks[DIV4_I],  MSTPCR0, 27, CLK_ENABLE_ON_INIT),
SH_CLK_MSTP32     148 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_FPU]    = SH_CLK_MSTP32(&div4_clks[DIV4_I],  MSTPCR0, 24, CLK_ENABLE_ON_INIT),
SH_CLK_MSTP32     149 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_INTC]   = SH_CLK_MSTP32(&div4_clks[DIV4_I],  MSTPCR0, 22, CLK_ENABLE_ON_INIT),
SH_CLK_MSTP32     150 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_DMAC0]  = SH_CLK_MSTP32(&div4_clks[DIV4_B],  MSTPCR0, 21, 0),
SH_CLK_MSTP32     151 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT),
SH_CLK_MSTP32     152 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_HUDI]   = SH_CLK_MSTP32(&div4_clks[DIV4_P],  MSTPCR0, 19, 0),
SH_CLK_MSTP32     153 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_UBC]    = SH_CLK_MSTP32(&div4_clks[DIV4_I],  MSTPCR0, 17, 0),
SH_CLK_MSTP32     154 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_TMU0]   = SH_CLK_MSTP32(&div4_clks[DIV4_P],  MSTPCR0, 15, 0),
SH_CLK_MSTP32     155 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_CMT]    = SH_CLK_MSTP32(&r_clk,		    MSTPCR0, 14, 0),
SH_CLK_MSTP32     156 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_RWDT]   = SH_CLK_MSTP32(&r_clk,		    MSTPCR0, 13, 0),
SH_CLK_MSTP32     157 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_DMAC1]  = SH_CLK_MSTP32(&div4_clks[DIV4_B],  MSTPCR0, 12, 0),
SH_CLK_MSTP32     158 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_TMU1]   = SH_CLK_MSTP32(&div4_clks[DIV4_P],  MSTPCR0, 11, 0),
SH_CLK_MSTP32     159 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_FLCTL]  = SH_CLK_MSTP32(&div4_clks[DIV4_P],  MSTPCR0, 10, 0),
SH_CLK_MSTP32     160 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_SCIF0]  = SH_CLK_MSTP32(&div4_clks[DIV4_P],  MSTPCR0, 9, 0),
SH_CLK_MSTP32     161 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_SCIF1]  = SH_CLK_MSTP32(&div4_clks[DIV4_P],  MSTPCR0, 8, 0),
SH_CLK_MSTP32     162 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_SCIF2]  = SH_CLK_MSTP32(&div4_clks[DIV4_P],  MSTPCR0, 7, 0),
SH_CLK_MSTP32     163 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_SCIF3]  = SH_CLK_MSTP32(&div4_clks[DIV4_B],  MSTPCR0, 6, 0),
SH_CLK_MSTP32     164 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_SCIF4]  = SH_CLK_MSTP32(&div4_clks[DIV4_B],  MSTPCR0, 5, 0),
SH_CLK_MSTP32     165 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_SCIF5]  = SH_CLK_MSTP32(&div4_clks[DIV4_B],  MSTPCR0, 4, 0),
SH_CLK_MSTP32     166 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_MSIOF0] = SH_CLK_MSTP32(&div4_clks[DIV4_B],  MSTPCR0, 2, 0),
SH_CLK_MSTP32     167 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_MSIOF1] = SH_CLK_MSTP32(&div4_clks[DIV4_B],  MSTPCR0, 1, 0),
SH_CLK_MSTP32     168 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_MERAM]  = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 0, 0),
SH_CLK_MSTP32     170 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_IIC]    = SH_CLK_MSTP32(&div4_clks[DIV4_P],  MSTPCR1, 9, 0),
SH_CLK_MSTP32     171 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_RTC]    = SH_CLK_MSTP32(&r_clk,		    MSTPCR1, 8, 0),
SH_CLK_MSTP32     173 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_ATAPI]  = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR2, 28, 0),
SH_CLK_MSTP32     174 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_ADC]    = SH_CLK_MSTP32(&div4_clks[DIV4_P],  MSTPCR2, 27, 0),
SH_CLK_MSTP32     175 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_TPU]    = SH_CLK_MSTP32(&div4_clks[DIV4_B],  MSTPCR2, 25, 0),
SH_CLK_MSTP32     176 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_IRDA]   = SH_CLK_MSTP32(&div4_clks[DIV4_P],  MSTPCR2, 24, 0),
SH_CLK_MSTP32     177 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_TSIF]   = SH_CLK_MSTP32(&div4_clks[DIV4_B],  MSTPCR2, 22, 0),
SH_CLK_MSTP32     178 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_ICB]    = SH_CLK_MSTP32(&div4_clks[DIV4_B],  MSTPCR2, 21, CLK_ENABLE_ON_INIT),
SH_CLK_MSTP32     179 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_SDHI0]  = SH_CLK_MSTP32(&div4_clks[DIV4_B],  MSTPCR2, 18, 0),
SH_CLK_MSTP32     180 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_SDHI1]  = SH_CLK_MSTP32(&div4_clks[DIV4_B],  MSTPCR2, 17, 0),
SH_CLK_MSTP32     181 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_KEYSC]  = SH_CLK_MSTP32(&r_clk,		    MSTPCR2, 14, 0),
SH_CLK_MSTP32     182 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_USB]    = SH_CLK_MSTP32(&div4_clks[DIV4_B],  MSTPCR2, 11, 0),
SH_CLK_MSTP32     183 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_2DG]    = SH_CLK_MSTP32(&div4_clks[DIV4_B],  MSTPCR2, 10, 0),
SH_CLK_MSTP32     184 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_SIU]    = SH_CLK_MSTP32(&div4_clks[DIV4_B],  MSTPCR2, 8, 0),
SH_CLK_MSTP32     185 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_VEU2H1] = SH_CLK_MSTP32(&div4_clks[DIV4_B],  MSTPCR2, 6, 0),
SH_CLK_MSTP32     186 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_VOU]    = SH_CLK_MSTP32(&div4_clks[DIV4_B],  MSTPCR2, 5, 0),
SH_CLK_MSTP32     187 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_BEU]    = SH_CLK_MSTP32(&div4_clks[DIV4_B],  MSTPCR2, 4, 0),
SH_CLK_MSTP32     188 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_CEU]    = SH_CLK_MSTP32(&div4_clks[DIV4_B],  MSTPCR2, 3, 0),
SH_CLK_MSTP32     189 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_VEU2H0] = SH_CLK_MSTP32(&div4_clks[DIV4_B],  MSTPCR2, 2, 0),
SH_CLK_MSTP32     190 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_VPU]    = SH_CLK_MSTP32(&div4_clks[DIV4_B],  MSTPCR2, 1, 0),
SH_CLK_MSTP32     191 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_LCDC]   = SH_CLK_MSTP32(&div4_clks[DIV4_B],  MSTPCR2, 0, 0),
SH_CLK_MSTP32     203 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_TLB] = SH_CLK_MSTP32(&div4_clks[DIV4_I],	    MSTPCR0, 31, CLK_ENABLE_ON_INIT),
SH_CLK_MSTP32     204 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_IC] = SH_CLK_MSTP32(&div4_clks[DIV4_I],	    MSTPCR0, 30, CLK_ENABLE_ON_INIT),
SH_CLK_MSTP32     205 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_OC] = SH_CLK_MSTP32(&div4_clks[DIV4_I],	    MSTPCR0, 29, CLK_ENABLE_ON_INIT),
SH_CLK_MSTP32     206 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_RSMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B],   MSTPCR0, 28, CLK_ENABLE_ON_INIT),
SH_CLK_MSTP32     207 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_ILMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_I],   MSTPCR0, 27, CLK_ENABLE_ON_INIT),
SH_CLK_MSTP32     208 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH],    MSTPCR0, 26, CLK_ENABLE_ON_INIT),
SH_CLK_MSTP32     209 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_FPU] = SH_CLK_MSTP32(&div4_clks[DIV4_I],	    MSTPCR0, 24, CLK_ENABLE_ON_INIT),
SH_CLK_MSTP32     210 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_INTC] = SH_CLK_MSTP32(&div4_clks[DIV4_P],    MSTPCR0, 22, CLK_ENABLE_ON_INIT),
SH_CLK_MSTP32     211 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_DMAC0] = SH_CLK_MSTP32(&div4_clks[DIV4_B],   MSTPCR0, 21, 0),
SH_CLK_MSTP32     212 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT),
SH_CLK_MSTP32     213 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_HUDI] = SH_CLK_MSTP32(&div4_clks[DIV4_P],    MSTPCR0, 19, 0),
SH_CLK_MSTP32     214 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_UBC] = SH_CLK_MSTP32(&div4_clks[DIV4_I],     MSTPCR0, 17, 0),
SH_CLK_MSTP32     215 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_TMU0] = SH_CLK_MSTP32(&div4_clks[DIV4_P],    MSTPCR0, 15, 0),
SH_CLK_MSTP32     216 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_CMT] = SH_CLK_MSTP32(&r_clk,		    MSTPCR0, 14, 0),
SH_CLK_MSTP32     217 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk,		    MSTPCR0, 13, 0),
SH_CLK_MSTP32     218 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_DMAC1] = SH_CLK_MSTP32(&div4_clks[DIV4_B],   MSTPCR0, 12, 0),
SH_CLK_MSTP32     219 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_TMU1] = SH_CLK_MSTP32(&div4_clks[DIV4_P],    MSTPCR0, 10, 0),
SH_CLK_MSTP32     220 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P],   MSTPCR0, 9, 0),
SH_CLK_MSTP32     221 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P],   MSTPCR0, 8, 0),
SH_CLK_MSTP32     222 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P],   MSTPCR0, 7, 0),
SH_CLK_MSTP32     223 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_SCIF3] = SH_CLK_MSTP32(&div4_clks[DIV4_B],   MSTPCR0, 6, 0),
SH_CLK_MSTP32     224 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_SCIF4] = SH_CLK_MSTP32(&div4_clks[DIV4_B],   MSTPCR0, 5, 0),
SH_CLK_MSTP32     225 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_SCIF5] = SH_CLK_MSTP32(&div4_clks[DIV4_B],   MSTPCR0, 4, 0),
SH_CLK_MSTP32     226 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_MSIOF0] = SH_CLK_MSTP32(&div4_clks[DIV4_B],  MSTPCR0, 2, 0),
SH_CLK_MSTP32     227 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_MSIOF1] = SH_CLK_MSTP32(&div4_clks[DIV4_B],  MSTPCR0, 1, 0),
SH_CLK_MSTP32     229 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk,		    MSTPCR1, 12, 0),
SH_CLK_MSTP32     230 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_RTC] = SH_CLK_MSTP32(&r_clk,		    MSTPCR1, 11, 0),
SH_CLK_MSTP32     231 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_IIC0] = SH_CLK_MSTP32(&div4_clks[DIV4_P],    MSTPCR1, 9, 0),
SH_CLK_MSTP32     232 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_IIC1] = SH_CLK_MSTP32(&div4_clks[DIV4_P],    MSTPCR1, 8, 0),
SH_CLK_MSTP32     234 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_MMC] = SH_CLK_MSTP32(&div4_clks[DIV4_B],	    MSTPCR2, 29, 0),
SH_CLK_MSTP32     235 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_ETHER] = SH_CLK_MSTP32(&div4_clks[DIV4_B],   MSTPCR2, 28, 0),
SH_CLK_MSTP32     236 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_ATAPI] = SH_CLK_MSTP32(&div4_clks[DIV4_B],   MSTPCR2, 26, 0),
SH_CLK_MSTP32     237 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_TPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B],	    MSTPCR2, 25, 0),
SH_CLK_MSTP32     238 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_IRDA] = SH_CLK_MSTP32(&div4_clks[DIV4_P],    MSTPCR2, 24, 0),
SH_CLK_MSTP32     239 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_TSIF] = SH_CLK_MSTP32(&div4_clks[DIV4_B],    MSTPCR2, 22, 0),
SH_CLK_MSTP32     240 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_USB1] = SH_CLK_MSTP32(&div4_clks[DIV4_B],    MSTPCR2, 21, 0),
SH_CLK_MSTP32     241 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_USB0] = SH_CLK_MSTP32(&div4_clks[DIV4_B],    MSTPCR2, 20, 0),
SH_CLK_MSTP32     242 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B],	    MSTPCR2, 19, 0),
SH_CLK_MSTP32     243 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_SDHI0] = SH_CLK_MSTP32(&div4_clks[DIV4_B],   MSTPCR2, 18, 0),
SH_CLK_MSTP32     244 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_SDHI1] = SH_CLK_MSTP32(&div4_clks[DIV4_B],   MSTPCR2, 17, 0),
SH_CLK_MSTP32     245 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_VEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B],    MSTPCR2, 15, 0),
SH_CLK_MSTP32     246 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_CEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B],    MSTPCR2, 13, 0),
SH_CLK_MSTP32     247 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_BEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B],    MSTPCR2, 12, 0),
SH_CLK_MSTP32     248 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_2DDMAC] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR2, 10, 0),
SH_CLK_MSTP32     249 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_SPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B],	    MSTPCR2, 9, 0),
SH_CLK_MSTP32     250 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_JPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B],	    MSTPCR2, 6, 0),
SH_CLK_MSTP32     251 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B],	    MSTPCR2, 5, 0),
SH_CLK_MSTP32     252 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_BEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B],    MSTPCR2, 4, 0),
SH_CLK_MSTP32     253 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_CEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B],    MSTPCR2, 3, 0),
SH_CLK_MSTP32     254 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_VEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B],    MSTPCR2, 2, 0),
SH_CLK_MSTP32     255 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B],	    MSTPCR2, 1, 0),
SH_CLK_MSTP32     256 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_B],    MSTPCR2, 0, 0),
SH_CLK_MSTP32     126 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0),
SH_CLK_MSTP32     127 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
SH_CLK_MSTP32     128 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
SH_CLK_MSTP32     129 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
SH_CLK_MSTP32     130 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
SH_CLK_MSTP32     131 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
SH_CLK_MSTP32     132 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
SH_CLK_MSTP32     133 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
SH_CLK_MSTP32     134 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP019] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
SH_CLK_MSTP32     135 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
SH_CLK_MSTP32     136 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
SH_CLK_MSTP32     137 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0),
SH_CLK_MSTP32     138 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP012] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 12, 0),
SH_CLK_MSTP32     139 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
SH_CLK_MSTP32     140 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
SH_CLK_MSTP32     141 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
SH_CLK_MSTP32     142 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
SH_CLK_MSTP32     143 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP007] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
SH_CLK_MSTP32     146 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP115] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 15, 0),
SH_CLK_MSTP32     147 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0),
SH_CLK_MSTP32     148 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP111] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 11, 0),
SH_CLK_MSTP32     149 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP109] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
SH_CLK_MSTP32     150 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP108] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 8, 0),
SH_CLK_MSTP32     151 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP107] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 7, 0),
SH_CLK_MSTP32     152 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP106] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 6, 0),
SH_CLK_MSTP32     153 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0),
SH_CLK_MSTP32     154 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 0, 0),
SH_CLK_MSTP32     157 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP331] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 31, 0),
SH_CLK_MSTP32     158 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP330] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 30, 0),
SH_CLK_MSTP32     159 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 23, 0),
SH_CLK_MSTP32     160 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0),
SH_CLK_MSTP32     161 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0),
SH_CLK_MSTP32     162 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0),
SH_CLK_MSTP32     163 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP319] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 19, 0),
SH_CLK_MSTP32     164 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP318] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 18, 0),
SH_CLK_MSTP32     165 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP317] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 17, 0),
SH_CLK_MSTP32     166 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP316] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 16, 0),
SH_CLK_MSTP32     167 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP315] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 15, 0),
SH_CLK_MSTP32     168 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 14, 0),
SH_CLK_MSTP32     169 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 13, 0),
SH_CLK_MSTP32     170 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP312] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 12, 0),
SH_CLK_MSTP32     171 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP304] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3,  4, 0),
SH_CLK_MSTP32     172 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP303] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3,  3, 0),
SH_CLK_MSTP32     173 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP302] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3,  2, 0),
SH_CLK_MSTP32     174 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP301] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3,  1, 0),
SH_CLK_MSTP32     175 arch/sh/kernel/cpu/sh4a/clock-sh7734.c 	[MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3,  0, 0),
SH_CLK_MSTP32      85 arch/sh/kernel/cpu/sh4a/clock-sh7757.c 	[MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
SH_CLK_MSTP32      86 arch/sh/kernel/cpu/sh4a/clock-sh7757.c 	[MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0),
SH_CLK_MSTP32      89 arch/sh/kernel/cpu/sh4a/clock-sh7757.c 	[MSTP127] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 27, 0),
SH_CLK_MSTP32      90 arch/sh/kernel/cpu/sh4a/clock-sh7757.c 	[MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0),
SH_CLK_MSTP32      91 arch/sh/kernel/cpu/sh4a/clock-sh7757.c 	[MSTP113] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 13, 0),
SH_CLK_MSTP32      92 arch/sh/kernel/cpu/sh4a/clock-sh7757.c 	[MSTP112] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 12, 0),
SH_CLK_MSTP32      93 arch/sh/kernel/cpu/sh4a/clock-sh7757.c 	[MSTP111] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 11, 0),
SH_CLK_MSTP32      94 arch/sh/kernel/cpu/sh4a/clock-sh7757.c 	[MSTP110] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 10, 0),
SH_CLK_MSTP32      95 arch/sh/kernel/cpu/sh4a/clock-sh7757.c 	[MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0),
SH_CLK_MSTP32      96 arch/sh/kernel/cpu/sh4a/clock-sh7757.c 	[MSTP102] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 2, 0),
SH_CLK_MSTP32      99 arch/sh/kernel/cpu/sh4a/clock-sh7757.c 	[MSTP220] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 20, 0),
SH_CLK_MSTP32      91 arch/sh/kernel/cpu/sh4a/clock-sh7785.c 	[MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
SH_CLK_MSTP32      92 arch/sh/kernel/cpu/sh4a/clock-sh7785.c 	[MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),
SH_CLK_MSTP32      93 arch/sh/kernel/cpu/sh4a/clock-sh7785.c 	[MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
SH_CLK_MSTP32      94 arch/sh/kernel/cpu/sh4a/clock-sh7785.c 	[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
SH_CLK_MSTP32      95 arch/sh/kernel/cpu/sh4a/clock-sh7785.c 	[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
SH_CLK_MSTP32      96 arch/sh/kernel/cpu/sh4a/clock-sh7785.c 	[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
SH_CLK_MSTP32      97 arch/sh/kernel/cpu/sh4a/clock-sh7785.c 	[MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
SH_CLK_MSTP32      98 arch/sh/kernel/cpu/sh4a/clock-sh7785.c 	[MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
SH_CLK_MSTP32      99 arch/sh/kernel/cpu/sh4a/clock-sh7785.c 	[MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
SH_CLK_MSTP32     100 arch/sh/kernel/cpu/sh4a/clock-sh7785.c 	[MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
SH_CLK_MSTP32     101 arch/sh/kernel/cpu/sh4a/clock-sh7785.c 	[MSTP013] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 13, 0),
SH_CLK_MSTP32     102 arch/sh/kernel/cpu/sh4a/clock-sh7785.c 	[MSTP012] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 12, 0),
SH_CLK_MSTP32     103 arch/sh/kernel/cpu/sh4a/clock-sh7785.c 	[MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
SH_CLK_MSTP32     104 arch/sh/kernel/cpu/sh4a/clock-sh7785.c 	[MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
SH_CLK_MSTP32     105 arch/sh/kernel/cpu/sh4a/clock-sh7785.c 	[MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
SH_CLK_MSTP32     106 arch/sh/kernel/cpu/sh4a/clock-sh7785.c 	[MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
SH_CLK_MSTP32     109 arch/sh/kernel/cpu/sh4a/clock-sh7785.c 	[MSTP119] = SH_CLK_MSTP32(NULL, MSTPCR1, 19, 0),
SH_CLK_MSTP32     110 arch/sh/kernel/cpu/sh4a/clock-sh7785.c 	[MSTP117] = SH_CLK_MSTP32(NULL, MSTPCR1, 17, 0),
SH_CLK_MSTP32     111 arch/sh/kernel/cpu/sh4a/clock-sh7785.c 	[MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
SH_CLK_MSTP32     112 arch/sh/kernel/cpu/sh4a/clock-sh7785.c 	[MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
SH_CLK_MSTP32     113 arch/sh/kernel/cpu/sh4a/clock-sh7785.c 	[MSTP100] = SH_CLK_MSTP32(NULL, MSTPCR1, 0, 0),
SH_CLK_MSTP32      92 arch/sh/kernel/cpu/sh4a/clock-sh7786.c 	[MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
SH_CLK_MSTP32      93 arch/sh/kernel/cpu/sh4a/clock-sh7786.c 	[MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),
SH_CLK_MSTP32      94 arch/sh/kernel/cpu/sh4a/clock-sh7786.c 	[MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
SH_CLK_MSTP32      95 arch/sh/kernel/cpu/sh4a/clock-sh7786.c 	[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
SH_CLK_MSTP32      96 arch/sh/kernel/cpu/sh4a/clock-sh7786.c 	[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
SH_CLK_MSTP32      97 arch/sh/kernel/cpu/sh4a/clock-sh7786.c 	[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
SH_CLK_MSTP32      98 arch/sh/kernel/cpu/sh4a/clock-sh7786.c 	[MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
SH_CLK_MSTP32      99 arch/sh/kernel/cpu/sh4a/clock-sh7786.c 	[MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
SH_CLK_MSTP32     100 arch/sh/kernel/cpu/sh4a/clock-sh7786.c 	[MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
SH_CLK_MSTP32     101 arch/sh/kernel/cpu/sh4a/clock-sh7786.c 	[MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
SH_CLK_MSTP32     102 arch/sh/kernel/cpu/sh4a/clock-sh7786.c 	[MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
SH_CLK_MSTP32     103 arch/sh/kernel/cpu/sh4a/clock-sh7786.c 	[MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
SH_CLK_MSTP32     104 arch/sh/kernel/cpu/sh4a/clock-sh7786.c 	[MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
SH_CLK_MSTP32     105 arch/sh/kernel/cpu/sh4a/clock-sh7786.c 	[MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0),
SH_CLK_MSTP32     106 arch/sh/kernel/cpu/sh4a/clock-sh7786.c 	[MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
SH_CLK_MSTP32     107 arch/sh/kernel/cpu/sh4a/clock-sh7786.c 	[MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
SH_CLK_MSTP32     108 arch/sh/kernel/cpu/sh4a/clock-sh7786.c 	[MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
SH_CLK_MSTP32     109 arch/sh/kernel/cpu/sh4a/clock-sh7786.c 	[MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
SH_CLK_MSTP32     110 arch/sh/kernel/cpu/sh4a/clock-sh7786.c 	[MSTP005] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
SH_CLK_MSTP32     111 arch/sh/kernel/cpu/sh4a/clock-sh7786.c 	[MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
SH_CLK_MSTP32     112 arch/sh/kernel/cpu/sh4a/clock-sh7786.c 	[MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
SH_CLK_MSTP32     115 arch/sh/kernel/cpu/sh4a/clock-sh7786.c 	[MSTP112] = SH_CLK_MSTP32(NULL, MSTPCR1, 12, 0),
SH_CLK_MSTP32     116 arch/sh/kernel/cpu/sh4a/clock-sh7786.c 	[MSTP110] = SH_CLK_MSTP32(NULL, MSTPCR1, 10, 0),
SH_CLK_MSTP32     117 arch/sh/kernel/cpu/sh4a/clock-sh7786.c 	[MSTP109] = SH_CLK_MSTP32(NULL, MSTPCR1, 9, 0),
SH_CLK_MSTP32     118 arch/sh/kernel/cpu/sh4a/clock-sh7786.c 	[MSTP108] = SH_CLK_MSTP32(NULL, MSTPCR1, 8, 0),
SH_CLK_MSTP32     119 arch/sh/kernel/cpu/sh4a/clock-sh7786.c 	[MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
SH_CLK_MSTP32     120 arch/sh/kernel/cpu/sh4a/clock-sh7786.c 	[MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
SH_CLK_MSTP32     121 arch/sh/kernel/cpu/sh4a/clock-sh7786.c 	[MSTP103] = SH_CLK_MSTP32(NULL, MSTPCR1, 3, 0),
SH_CLK_MSTP32     122 arch/sh/kernel/cpu/sh4a/clock-sh7786.c 	[MSTP102] = SH_CLK_MSTP32(NULL, MSTPCR1, 2, 0),
SH_CLK_MSTP32      83 arch/sh/kernel/cpu/sh4a/clock-shx3.c 	[MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
SH_CLK_MSTP32      84 arch/sh/kernel/cpu/sh4a/clock-shx3.c 	[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
SH_CLK_MSTP32      85 arch/sh/kernel/cpu/sh4a/clock-shx3.c 	[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
SH_CLK_MSTP32      86 arch/sh/kernel/cpu/sh4a/clock-shx3.c 	[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
SH_CLK_MSTP32      87 arch/sh/kernel/cpu/sh4a/clock-shx3.c 	[MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
SH_CLK_MSTP32      88 arch/sh/kernel/cpu/sh4a/clock-shx3.c 	[MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
SH_CLK_MSTP32      89 arch/sh/kernel/cpu/sh4a/clock-shx3.c 	[MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
SH_CLK_MSTP32      90 arch/sh/kernel/cpu/sh4a/clock-shx3.c 	[MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
SH_CLK_MSTP32      91 arch/sh/kernel/cpu/sh4a/clock-shx3.c 	[MSTP001] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
SH_CLK_MSTP32      92 arch/sh/kernel/cpu/sh4a/clock-shx3.c 	[MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0),
SH_CLK_MSTP32      95 arch/sh/kernel/cpu/sh4a/clock-shx3.c 	[MSTP119] = SH_CLK_MSTP32(NULL, MSTPCR1, 19, 0),
SH_CLK_MSTP32      96 arch/sh/kernel/cpu/sh4a/clock-shx3.c 	[MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
SH_CLK_MSTP32      97 arch/sh/kernel/cpu/sh4a/clock-shx3.c 	[MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),