SHA1_H4            82 arch/mips/cavium-octeon/crypto/octeon-sha1.c 	sctx->state[4] = SHA1_H4;
SHA1_H4            67 arch/powerpc/crypto/sha1-spe-glue.c 	sctx->state[4] = SHA1_H4;
SHA1_H4            31 arch/powerpc/crypto/sha1.c 		.state = { SHA1_H0, SHA1_H1, SHA1_H2, SHA1_H3, SHA1_H4 },
SHA1_H4            38 arch/s390/crypto/sha1_s390.c 	sctx->state[4] = SHA1_H4;
SHA1_H4            35 arch/sparc/crypto/sha1_glue.c 		.state = { SHA1_H0, SHA1_H1, SHA1_H2, SHA1_H3, SHA1_H4 },
SHA1_H4            24 drivers/crypto/ccp/ccp-ops.c 	cpu_to_be32(SHA1_H4),
SHA1_H4            33 drivers/crypto/ccree/cc_hash.c 	SHA1_H4, SHA1_H3, SHA1_H2, SHA1_H1, SHA1_H0 };
SHA1_H4           337 drivers/crypto/chelsio/chcr_algo.h 		SHA1_H0, SHA1_H1, SHA1_H2, SHA1_H3, SHA1_H4,
SHA1_H4           940 drivers/crypto/marvell/hash.c 	creq->state[4] = SHA1_H4;
SHA1_H4          1293 drivers/crypto/n2_core.c 	SHA1_H0, SHA1_H1, SHA1_H2, SHA1_H3, SHA1_H4,
SHA1_H4           279 drivers/crypto/padlock-sha.c 		.state = { SHA1_H0, SHA1_H1, SHA1_H2, SHA1_H3, SHA1_H4 },
SHA1_H4            21 drivers/crypto/qce/sha.c 	SHA1_H0, SHA1_H1, SHA1_H2, SHA1_H3, SHA1_H4, 0, 0, 0
SHA1_H4           109 drivers/crypto/sunxi-ss/sun4i-ss-hash.c 		octx->state[4] = SHA1_H4;
SHA1_H4            28 include/crypto/sha1_base.h 	sctx->state[4] = SHA1_H4;