SHA1_H2            80 arch/mips/cavium-octeon/crypto/octeon-sha1.c 	sctx->state[2] = SHA1_H2;
SHA1_H2            65 arch/powerpc/crypto/sha1-spe-glue.c 	sctx->state[2] = SHA1_H2;
SHA1_H2            31 arch/powerpc/crypto/sha1.c 		.state = { SHA1_H0, SHA1_H1, SHA1_H2, SHA1_H3, SHA1_H4 },
SHA1_H2            36 arch/s390/crypto/sha1_s390.c 	sctx->state[2] = SHA1_H2;
SHA1_H2            35 arch/sparc/crypto/sha1_glue.c 		.state = { SHA1_H0, SHA1_H1, SHA1_H2, SHA1_H3, SHA1_H4 },
SHA1_H2            23 drivers/crypto/ccp/ccp-ops.c 	cpu_to_be32(SHA1_H2), cpu_to_be32(SHA1_H3),
SHA1_H2            31 drivers/crypto/ccree/cc_hash.c 	SHA1_H3, SHA1_H2, SHA1_H1, SHA1_H0 };
SHA1_H2            33 drivers/crypto/ccree/cc_hash.c 	SHA1_H4, SHA1_H3, SHA1_H2, SHA1_H1, SHA1_H0 };
SHA1_H2           337 drivers/crypto/chelsio/chcr_algo.h 		SHA1_H0, SHA1_H1, SHA1_H2, SHA1_H3, SHA1_H4,
SHA1_H2           938 drivers/crypto/marvell/hash.c 	creq->state[2] = SHA1_H2;
SHA1_H2          1293 drivers/crypto/n2_core.c 	SHA1_H0, SHA1_H1, SHA1_H2, SHA1_H3, SHA1_H4,
SHA1_H2           279 drivers/crypto/padlock-sha.c 		.state = { SHA1_H0, SHA1_H1, SHA1_H2, SHA1_H3, SHA1_H4 },
SHA1_H2            21 drivers/crypto/qce/sha.c 	SHA1_H0, SHA1_H1, SHA1_H2, SHA1_H3, SHA1_H4, 0, 0, 0
SHA1_H2            65 drivers/crypto/sunxi-ss/sun4i-ss-hash.c 		octx->hash[2] = SHA1_H2;
SHA1_H2           107 drivers/crypto/sunxi-ss/sun4i-ss-hash.c 		octx->state[2] = SHA1_H2;
SHA1_H2            26 include/crypto/sha1_base.h 	sctx->state[2] = SHA1_H2;