SFB 130 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\ SFB 131 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_CONTROL, GRPH_BANK_WIDTH, mask_sh),\ SFB 132 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_CONTROL, GRPH_BANK_HEIGHT, mask_sh),\ SFB 133 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, mask_sh),\ SFB 134 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_CONTROL, GRPH_TILE_SPLIT, mask_sh),\ SFB 135 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_CONTROL, GRPH_MICRO_TILE_MODE, mask_sh),\ SFB 136 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_CONTROL, GRPH_PIPE_CONFIG, mask_sh),\ SFB 137 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_CONTROL, GRPH_ARRAY_MODE, mask_sh),\ SFB 138 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE, mask_sh) SFB 141 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_ENABLE, GRPH_ENABLE, mask_sh),\ SFB 142 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_CONTROL, GRPH_DEPTH, mask_sh),\ SFB 143 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_CONTROL, GRPH_FORMAT, mask_sh),\ SFB 144 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\ SFB 145 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_X_START, GRPH_X_START, mask_sh),\ SFB 146 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_Y_START, GRPH_Y_START, mask_sh),\ SFB 147 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_X_END, GRPH_X_END, mask_sh),\ SFB 148 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_Y_END, GRPH_Y_END, mask_sh),\ SFB 149 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_PITCH, GRPH_PITCH, mask_sh),\ SFB 150 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, HW_ROTATION, GRPH_ROTATION_ANGLE, mask_sh),\ SFB 151 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, mask_sh),\ SFB 152 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, mask_sh),\ SFB 153 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_SELECT, mask_sh),\ SFB 154 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_R_SIGN, mask_sh),\ SFB 155 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_G_SIGN, mask_sh),\ SFB 156 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_B_SIGN, mask_sh),\ SFB 157 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\ SFB 158 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_SECONDARY_SURFACE_ADDRESS, GRPH_SECONDARY_SURFACE_ADDRESS, mask_sh),\ SFB 159 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\ SFB 160 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_PRIMARY_SURFACE_ADDRESS, GRPH_PRIMARY_SURFACE_ADDRESS, mask_sh),\ SFB 161 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING, mask_sh),\ SFB 162 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_UPDATE, GRPH_UPDATE_LOCK, mask_sh),\ SFB 163 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_H_RETRACE_EN, mask_sh) SFB 166 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, mask_sh) SFB 169 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DVMM_PTE_CONTROL, DVMM_PAGE_WIDTH, mask_sh),\ SFB 170 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DVMM_PTE_CONTROL, DVMM_PAGE_HEIGHT, mask_sh),\ SFB 171 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DVMM_PTE_CONTROL, DVMM_MIN_PTE_BEFORE_FLIP, mask_sh),\ SFB 172 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DVMM_PTE_ARB_CONTROL, DVMM_PTE_REQ_PER_CHUNK, mask_sh),\ SFB 173 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DVMM_PTE_ARB_CONTROL, DVMM_MAX_PTE_REQ_OUTSTANDING, mask_sh) SFB 176 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_ARBITRATION_CONTROL1, PIXEL_DURATION, mask_sh),\ SFB 177 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, mask_sh),\ SFB 178 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_WATERMARK_MASK_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK, mask_sh),\ SFB 179 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, mask_sh),\ SFB 180 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, mask_sh),\ SFB 181 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE, mask_sh),\ SFB 182 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_IGNORE_FBC, mask_sh),\ SFB 187 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK, mask_sh),\ SFB 188 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_WATERMARK_MASK_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\ SFB 189 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_ENABLE, mask_sh),\ SFB 190 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\ SFB 191 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, mask_sh),\ SFB 192 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_WATERMARK, mask_sh) SFB 209 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_CONTROL, GRPH_SW_MODE, mask_sh),\ SFB 210 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_CONTROL, GRPH_SE_ENABLE, mask_sh),\ SFB 211 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_CONTROL, GRPH_NUM_SHADER_ENGINES, mask_sh),\ SFB 212 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_CONTROL, GRPH_NUM_PIPES, mask_sh),\ SFB 213 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE, mask_sh) SFB 216 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_STUTTER_CONTROL2, STUTTER_EXIT_SELF_REFRESH_WATERMARK, mask_sh),\ SFB 217 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_STUTTER_CONTROL2, STUTTER_ENTER_SELF_REFRESH_WATERMARK, mask_sh),\ SFB 218 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_URGENT_LEVEL_CONTROL, URGENT_LEVEL_LOW_WATERMARK, mask_sh),\ SFB 219 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_URGENT_LEVEL_CONTROL, URGENT_LEVEL_HIGH_WATERMARK, mask_sh),\ SFB 220 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, mask_sh),\ SFB 221 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, mask_sh),\ SFB 222 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_WATERMARK_MASK_CONTROL, PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\ SFB 223 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_ENABLE, mask_sh),\ SFB 224 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\ SFB 225 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, mask_sh),\ SFB 226 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_WATERMARK, mask_sh)