SF 1956 arch/s390/kernel/perf_cpum_sf.c CPUMF_EVENT_ATTR(SF, SF_CYCLES_BASIC, PERF_EVENT_CPUM_SF); SF 1957 arch/s390/kernel/perf_cpum_sf.c CPUMF_EVENT_ATTR(SF, SF_CYCLES_BASIC_DIAG, PERF_EVENT_CPUM_SF_DIAG); SF 1982 arch/s390/kernel/perf_cpum_sf.c [SF_CYCLES_BASIC_ATTR_IDX] = CPUMF_EVENT_PTR(SF, SF_CYCLES_BASIC) SF 2187 arch/s390/kernel/perf_cpum_sf.c CPUMF_EVENT_PTR(SF, SF_CYCLES_BASIC_DIAG); SF 593 arch/x86/kernel/uprobes.c COND(78, 79, XF(SF)) \ SF 596 arch/x86/kernel/uprobes.c COND(7c, 7d, XF(SF) != XF(OF)) \ SF 597 arch/x86/kernel/uprobes.c COND(7e, 7f, XF(ZF) || XF(SF) != XF(OF)) SF 49 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\ SF 50 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\ SF 51 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO2_USE_512FBR_DTO, mask_sh),\ SF 52 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_USE_512FBR_DTO, mask_sh),\ SF 53 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO1_USE_512FBR_DTO, mask_sh),\ SF 54 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh),\ SF 55 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\ SF 56 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h SF(DCCG_AUDIO_DTO1_MODULE, DCCG_AUDIO_DTO1_MODULE, mask_sh),\ SF 57 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h SF(DCCG_AUDIO_DTO1_PHASE, DCCG_AUDIO_DTO1_PHASE, mask_sh),\ SF 58 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, AUDIO_RATE_CAPABILITIES, mask_sh),\ SF 59 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, CLKSTOP, mask_sh),\ SF 60 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, EPSS, mask_sh) SF 64 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h SF(AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ SF 65 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h SF(AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh) SF 451 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) SF 495 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\ SF 503 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\ SF 504 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\ SF 505 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\ SF 506 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\ SF 507 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh) SF 183 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, mask_sh),\ SF 184 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED, mask_sh) SF 229 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\ SF 230 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\ SF 231 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\ SF 232 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\ SF 233 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh) SF 237 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SF(DCP0_GRPH_SECONDARY_SURFACE_ADDRESS, GRPH_SECONDARY_DFQ_ENABLE, mask_sh),\ SF 347 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ SF 348 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ SF 87 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(CNV0_WB_ENABLE, WB_ENABLE, mask_sh),\ SF 88 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(CNV0_WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\ SF 89 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\ SF 90 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\ SF 91 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(CNV0_WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\ SF 92 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(CNV0_WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\ SF 93 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(CNV0_CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\ SF 94 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(CNV0_CNV_MODE, CNV_STEREO_TYPE, mask_sh),\ SF 95 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(CNV0_CNV_MODE, CNV_INTERLACED_MODE, mask_sh),\ SF 96 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(CNV0_CNV_MODE, CNV_EYE_SELECTION, mask_sh),\ SF 97 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(CNV0_CNV_MODE, CNV_STEREO_POLARITY, mask_sh),\ SF 98 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(CNV0_CNV_MODE, CNV_INTERLACED_FIELD_ORDER, mask_sh),\ SF 99 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(CNV0_CNV_MODE, CNV_STEREO_SPLIT, mask_sh),\ SF 100 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(CNV0_CNV_MODE, CNV_NEW_CONTENT, mask_sh),\ SF 101 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(CNV0_CNV_MODE, CNV_FRAME_CAPTURE_EN, mask_sh),\ SF 102 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(CNV0_WB_SOFT_RESET, WB_SOFT_RESET, mask_sh),\ SF 103 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\ SF 104 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_DUALSIZE_REQ, mask_sh),\ SF 105 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\ SF 106 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\ SF 107 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\ SF 108 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\ SF 109 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\ SF 110 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, mask_sh),\ SF 111 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\ SF 112 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\ SF 113 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_CHROMA_PITCH, mask_sh),\ SF 114 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE, mask_sh),\ SF 115 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, mask_sh),\ SF 116 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, WM_CHANGE_ACK_FORCE_ON, mask_sh),\ SF 117 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, mask_sh),\ SF 118 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, mask_sh),\ SF 119 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB_BUF_1_ADDR_Y_OFFSET, mask_sh),\ SF 120 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, mask_sh),\ SF 121 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB_BUF_1_ADDR_C_OFFSET, mask_sh),\ SF 122 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, mask_sh),\ SF 123 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB_BUF_2_ADDR_Y_OFFSET, mask_sh),\ SF 124 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, mask_sh),\ SF 125 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB_BUF_2_ADDR_C_OFFSET, mask_sh),\ SF 126 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, mask_sh),\ SF 127 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB_BUF_3_ADDR_Y_OFFSET, mask_sh),\ SF 128 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, mask_sh),\ SF 129 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB_BUF_3_ADDR_C_OFFSET, mask_sh),\ SF 130 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, mask_sh),\ SF 131 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB_BUF_4_ADDR_Y_OFFSET, mask_sh),\ SF 132 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, mask_sh),\ SF 133 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB_BUF_4_ADDR_C_OFFSET, mask_sh),\ SF 134 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK_IGNORE, mask_sh),\ SF 135 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_EN, mask_sh),\ SF 136 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_ACK, mask_sh),\ SF 137 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN, mask_sh),\ SF 138 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK, mask_sh),\ SF 139 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, mask_sh),\ SF 140 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_REFRESH_WATERMARK, mask_sh),\ SF 141 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\ SF 142 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_FORCE_ON, mask_sh),\ SF 143 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_ALLOW_FOR_URGENT, mask_sh),\ SF 144 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\ SF 145 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, mask_sh),\ SF 146 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_WARM_UP_CNTL, MCIF_WB_PITCH_SIZE_WARMUP, mask_sh),\ SF 147 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, mask_sh),\ SF 148 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h SF(MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, mask_sh) SF 61 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_TOP_SEL, MPCC_TOP_SEL, mask_sh),\ SF 62 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_BOT_SEL, MPCC_BOT_SEL, mask_sh),\ SF 63 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_CONTROL, MPCC_MODE, mask_sh),\ SF 64 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_BLND_MODE, mask_sh),\ SF 65 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_MULTIPLIED_MODE, mask_sh),\ SF 66 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_CONTROL, MPCC_BLND_ACTIVE_OVERLAP_ONLY, mask_sh),\ SF 67 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_CONTROL, MPCC_GLOBAL_ALPHA, mask_sh),\ SF 68 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_CONTROL, MPCC_GLOBAL_GAIN, mask_sh),\ SF 69 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_STATUS, MPCC_IDLE, mask_sh),\ SF 70 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_STATUS, MPCC_BUSY, mask_sh),\ SF 71 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_OPP_ID, MPCC_OPP_ID, mask_sh),\ SF 72 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_BG_G_Y, MPCC_BG_G_Y, mask_sh),\ SF 73 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_BG_R_CR, MPCC_BG_R_CR, mask_sh),\ SF 74 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_BG_B_CB, MPCC_BG_B_CB, mask_sh),\ SF 75 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_EN, mask_sh),\ SF 76 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_MODE, mask_sh),\ SF 77 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FRAME_ALT, mask_sh),\ SF 78 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FIELD_ALT, mask_sh),\ SF 79 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FORCE_NEXT_FRAME_POL, mask_sh),\ SF 80 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FORCE_NEXT_TOP_POL, mask_sh),\ SF 81 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h SF(MPC_OUT0_MUX, MPC_OUT_MUX, mask_sh) SF 178 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\ SF 179 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\ SF 180 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\ SF 181 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\ SF 182 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DATA_EN, mask_sh),\ SF 183 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DE_MODE, mask_sh),\ SF 184 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_BLANK_CONTROL, OTG_CURRENT_BLANK_STATE, mask_sh),\ SF 185 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\ SF 186 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\ SF 187 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_GLOBAL_CONTROL0, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\ SF 188 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\ SF 189 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_BLANK_DATA_DOUBLE_BUFFER_EN, mask_sh),\ SF 190 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\ SF 191 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\ SF 192 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\ SF 193 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\ SF 194 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\ SF 195 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\ SF 196 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_BY2, mask_sh),\ SF 197 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\ SF 198 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\ SF 199 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\ SF 200 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\ SF 201 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\ SF 202 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\ SF 203 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_INTERLACE_CONTROL, OTG_INTERLACE_ENABLE, mask_sh),\ SF 204 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\ SF 205 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\ SF 206 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\ SF 207 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\ SF 208 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\ SF 209 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\ SF 210 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\ SF 211 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\ SF 212 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\ SF 213 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\ SF 214 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\ SF 215 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\ SF 216 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\ SF 217 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\ SF 218 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\ SF 219 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_V_TOTAL_MID, OTG_V_TOTAL_MID, mask_sh),\ SF 220 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\ SF 221 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\ SF 222 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\ SF 223 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\ SF 224 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK_EN, mask_sh),\ SF 225 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\ SF 226 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\ SF 227 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_FRAME_NUM, mask_sh),\ SF 228 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\ SF 229 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\ SF 230 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\ SF 231 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\ SF 232 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\ SF 233 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\ SF 234 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\ SF 235 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\ SF 236 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\ SF 237 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\ SF 238 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\ SF 239 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\ SF 240 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\ SF 241 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\ SF 242 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\ SF 243 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\ SF 244 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\ SF 245 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\ SF 246 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\ SF 247 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\ SF 248 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_B_CB, mask_sh),\ SF 249 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_G_Y, mask_sh),\ SF 250 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_R_CR, mask_sh),\ SF 251 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\ SF 252 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\ SF 253 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\ SF 254 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\ SF 255 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\ SF 256 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\ SF 257 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\ SF 258 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\ SF 259 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\ SF 260 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\ SF 261 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\ SF 262 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\ SF 263 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\ SF 264 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\ SF 265 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\ SF 266 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\ SF 267 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\ SF 268 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\ SF 269 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\ SF 270 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\ SF 271 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\ SF 272 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\ SF 273 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_MASTER_UPDATE_MODE, MASTER_UPDATE_INTERLACED_MODE, mask_sh),\ SF 274 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\ SF 275 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\ SF 276 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\ SF 277 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\ SF 278 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\ SF 279 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\ SF 280 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\ SF 281 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\ SF 282 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\ SF 283 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\ SF 284 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\ SF 285 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\ SF 286 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\ SF 287 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\ SF 288 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\ SF 289 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\ SF 290 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\ SF 291 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\ SF 292 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\ SF 293 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\ SF 294 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\ SF 295 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\ SF 296 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\ SF 297 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh) SF 301 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC0, mask_sh),\ SF 302 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC1, mask_sh),\ SF 303 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_VRES, mask_sh),\ SF 304 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_HRES, mask_sh),\ SF 305 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_RAMP0_OFFSET, mask_sh),\ SF 306 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_EN, mask_sh),\ SF 307 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_MODE, mask_sh),\ SF 308 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_DYNAMIC_RANGE, mask_sh),\ SF 309 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_COLOR_FORMAT, mask_sh),\ SF 310 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_MASK, mask_sh),\ SF 311 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_DATA, mask_sh),\ SF 312 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SRC_SEL, mask_sh),\ SF 313 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_MANUAL_FLOW_CONTROL, MANUAL_FLOW_CONTROL, mask_sh),\ SF 265 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ SF 266 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ SF 106 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_ENABLE, WB_ENABLE, mask_sh),\ SF 107 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\ SF 108 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\ SF 109 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\ SF 110 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_EC_CONFIG, WB_TEST_CLK_SEL, mask_sh),\ SF 111 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\ SF 112 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_EC_CONFIG, WB_LB_SD_DIS, mask_sh),\ SF 113 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\ SF 114 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_MODE_SEL, mask_sh),\ SF 115 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_DIS, mask_sh),\ SF 116 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_FORCE, mask_sh),\ SF 117 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_STATE, mask_sh),\ SF 118 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_EC_CONFIG, WB_RAM_PW_SAVE_MODE, mask_sh),\ SF 119 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_EC_CONFIG, WBSCL_LUT_MEM_PWR_STATE, mask_sh),\ SF 120 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_MODE, CNV_OUT_BPC, mask_sh),\ SF 121 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_MODE, CNV_FRAME_CAPTURE_RATE, mask_sh),\ SF 122 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\ SF 123 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_MODE, CNV_STEREO_TYPE, mask_sh),\ SF 124 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_MODE, CNV_INTERLACED_MODE, mask_sh),\ SF 125 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_MODE, CNV_EYE_SELECTION, mask_sh),\ SF 126 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_MODE, CNV_STEREO_POLARITY, mask_sh),\ SF 127 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_MODE, CNV_INTERLACED_FIELD_ORDER, mask_sh),\ SF 128 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_MODE, CNV_STEREO_SPLIT, mask_sh),\ SF 129 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_MODE, CNV_NEW_CONTENT, mask_sh),\ SF 130 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_MODE, CNV_FRAME_CAPTURE_EN_CURRENT, mask_sh),\ SF 131 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_MODE, CNV_FRAME_CAPTURE_EN, mask_sh),\ SF 132 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_WINDOW_START, CNV_WINDOW_START_X, mask_sh),\ SF 133 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_WINDOW_START, CNV_WINDOW_START_Y, mask_sh),\ SF 134 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_WINDOW_SIZE, CNV_WINDOW_WIDTH, mask_sh),\ SF 135 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_WINDOW_SIZE, CNV_WINDOW_HEIGHT, mask_sh),\ SF 136 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_UPDATE, CNV_UPDATE_PENDING, mask_sh),\ SF 137 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_UPDATE, CNV_UPDATE_TAKEN, mask_sh),\ SF 138 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_UPDATE, CNV_UPDATE_LOCK, mask_sh),\ SF 139 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_SOURCE_SIZE, CNV_SOURCE_WIDTH, mask_sh),\ SF 140 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_SOURCE_SIZE, CNV_SOURCE_HEIGHT, mask_sh),\ SF 141 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_TEST_CNTL, CNV_TEST_CRC_EN, mask_sh),\ SF 142 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_TEST_CNTL, CNV_TEST_CRC_CONT_EN, mask_sh),\ SF 143 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_TEST_CRC_RED, CNV_TEST_CRC_RED_MASK, mask_sh),\ SF 144 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_TEST_CRC_RED, CNV_TEST_CRC_SIG_RED, mask_sh),\ SF 145 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_TEST_CRC_GREEN, CNV_TEST_CRC_GREEN_MASK, mask_sh),\ SF 146 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_TEST_CRC_GREEN, CNV_TEST_CRC_SIG_GREEN, mask_sh),\ SF 147 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_TEST_CRC_BLUE, CNV_TEST_CRC_BLUE_MASK, mask_sh),\ SF 148 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_TEST_CRC_BLUE, CNV_TEST_CRC_SIG_BLUE, mask_sh),\ SF 149 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_DEBUG_CTRL, WB_DEBUG_EN, mask_sh),\ SF 150 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_DEBUG_CTRL, WB_DEBUG_SEL, mask_sh),\ SF 151 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_DBG_MODE, WB_DBG_MODE_EN, mask_sh),\ SF 152 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_DBG_MODE, WB_DBG_DIN_FMT, mask_sh),\ SF 153 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_DBG_MODE, WB_DBG_36MODE, mask_sh),\ SF 154 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_DBG_MODE, WB_DBG_CMAP, mask_sh),\ SF 155 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_DBG_MODE, WB_DBG_PXLRATE_ERROR, mask_sh),\ SF 156 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_DBG_MODE, WB_DBG_SOURCE_WIDTH, mask_sh),\ SF 157 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_HW_DEBUG, WB_HW_DEBUG, mask_sh),\ SF 158 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_SOFT_RESET, WB_SOFT_RESET, mask_sh),\ SF 159 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_TEST_DEBUG_INDEX, CNV_TEST_DEBUG_INDEX, mask_sh),\ SF 160 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_TEST_DEBUG_INDEX, CNV_TEST_DEBUG_WRITE_EN, mask_sh),\ SF 161 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(CNV_TEST_DEBUG_DATA, CNV_TEST_DEBUG_DATA, mask_sh),\ SF 162 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\ SF 163 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_PHASE, mask_sh),\ SF 164 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_FILTER_TYPE, mask_sh),\ SF 165 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\ SF 166 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\ SF 167 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\ SF 168 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\ SF 169 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_MODE, WBSCL_MODE, mask_sh),\ SF 170 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_MODE, WBSCL_OUT_BIT_DEPTH, mask_sh),\ SF 171 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_Y_RGB, mask_sh),\ SF 172 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_CBCR, mask_sh),\ SF 173 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_Y_RGB, mask_sh),\ SF 174 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_CBCR, mask_sh),\ SF 175 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_DEST_SIZE, WBSCL_DEST_HEIGHT, mask_sh),\ SF 176 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_DEST_SIZE, WBSCL_DEST_WIDTH, mask_sh),\ SF 177 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL_H_SCALE_RATIO, mask_sh),\ SF 178 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_FRAC_Y_RGB, mask_sh),\ SF 179 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_INT_Y_RGB, mask_sh),\ SF 180 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_FRAC_CBCR, mask_sh),\ SF 181 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_INT_CBCR, mask_sh),\ SF 182 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL_V_SCALE_RATIO, mask_sh),\ SF 183 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_FRAC_Y_RGB, mask_sh),\ SF 184 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_INT_Y_RGB, mask_sh),\ SF 185 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL_V_INIT_FRAC_CBCR, mask_sh),\ SF 186 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL_V_INIT_INT_CBCR, mask_sh),\ SF 187 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_Y_RGB, mask_sh),\ SF 188 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_CBCR, mask_sh),\ SF 189 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_FLAG, mask_sh),\ SF 190 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_ACK, mask_sh),\ SF 191 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_MASK, mask_sh),\ SF 192 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_INT_STATUS, mask_sh),\ SF 193 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_INT_TYPE, mask_sh),\ SF 194 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_FLAG, mask_sh),\ SF 195 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_ACK, mask_sh),\ SF 196 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_MASK, mask_sh),\ SF 197 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_INT_STATUS, mask_sh),\ SF 198 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_INT_TYPE, mask_sh),\ SF 199 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_TEST_CNTL, WBSCL_TEST_CRC_EN, mask_sh),\ SF 200 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_TEST_CNTL, WBSCL_TEST_CRC_CONT_EN, mask_sh),\ SF 201 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_TEST_CRC_RED, WBSCL_TEST_CRC_RED_MASK, mask_sh),\ SF 202 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_TEST_CRC_RED, WBSCL_TEST_CRC_SIG_RED, mask_sh),\ SF 203 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_TEST_CRC_GREEN, WBSCL_TEST_CRC_GREEN_MASK, mask_sh),\ SF 204 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_TEST_CRC_GREEN, WBSCL_TEST_CRC_SIG_GREEN, mask_sh),\ SF 205 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_TEST_CRC_BLUE, WBSCL_TEST_CRC_BLUE_MASK, mask_sh),\ SF 206 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_TEST_CRC_BLUE, WBSCL_TEST_CRC_SIG_BLUE, mask_sh),\ SF 207 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_BACKPRESSURE_CNT_EN, WBSCL_BACKPRESSURE_CNT_EN, mask_sh),\ SF 208 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_MCIF_BACKPRESSURE_CNT, WB_MCIF_Y_MAX_BACKPRESSURE, mask_sh),\ SF 209 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_MCIF_BACKPRESSURE_CNT, WB_MCIF_C_MAX_BACKPRESSURE, mask_sh),\ SF 210 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_CLAMP_Y_RGB, WBSCL_CLAMP_UPPER_Y_RGB, mask_sh),\ SF 211 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_CLAMP_Y_RGB, WBSCL_CLAMP_LOWER_Y_RGB, mask_sh),\ SF 212 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_UPPER_CBCR, mask_sh),\ SF 213 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_LOWER_CBCR, mask_sh),\ SF 214 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL_OUTSIDE_PIX_STRATEGY, mask_sh),\ SF 215 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL_BLACK_COLOR_G_Y, mask_sh),\ SF 216 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL_BLACK_COLOR_B_CB, mask_sh),\ SF 217 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL_BLACK_COLOR_R_CR, mask_sh),\ SF 218 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_DEBUG, WBSCL_DEBUG, mask_sh),\ SF 219 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_TEST_DEBUG_INDEX, WBSCL_TEST_DEBUG_INDEX, mask_sh),\ SF 220 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_TEST_DEBUG_INDEX, WBSCL_TEST_DEBUG_WRITE_EN, mask_sh),\ SF 221 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_TEST_DEBUG_DATA, WBSCL_TEST_DEBUG_DATA, mask_sh),\ SF 222 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_WARM_UP_MODE_CTL1, WIDTH_WARMUP, mask_sh),\ SF 223 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_WARM_UP_MODE_CTL1, HEIGHT_WARMUP, mask_sh),\ SF 224 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_WARM_UP_MODE_CTL1, GMC_WARM_UP_ENABLE, mask_sh),\ SF 225 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_WARM_UP_MODE_CTL2, DATA_VALUE_WARMUP, mask_sh),\ SF 226 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_WARM_UP_MODE_CTL2, MODE_WARMUP, mask_sh),\ SF 227 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WB_WARM_UP_MODE_CTL2, DATA_DEPTH_WARMUP, mask_sh) SF 118 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\ SF 119 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\ SF 120 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\ SF 121 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\ SF 122 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\ SF 123 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\ SF 124 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, mask_sh),\ SF 125 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\ SF 126 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R, MCIF_WB_BUFMGR_CUR_LINE_R, mask_sh),\ SF 127 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_VCE_INT_STATUS, mask_sh),\ SF 128 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_INT_STATUS, mask_sh),\ SF 129 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS, mask_sh),\ SF 130 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_CUR_BUF, mask_sh),\ SF 131 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_BUFTAG, mask_sh),\ SF 132 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_CUR_LINE_L, mask_sh),\ SF 133 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_NEXT_BUF, mask_sh),\ SF 134 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\ SF 135 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_CHROMA_PITCH, mask_sh),\ SF 136 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_ACTIVE, mask_sh),\ SF 137 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_SW_LOCKED, mask_sh),\ SF 138 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_VCE_LOCKED, mask_sh),\ SF 139 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_OVERFLOW, mask_sh),\ SF 140 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_DISABLE, mask_sh),\ SF 141 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_MODE, mask_sh),\ SF 142 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_BUFTAG, mask_sh),\ SF 143 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_NXT_BUF, mask_sh),\ SF 144 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_FIELD, mask_sh),\ SF 145 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_CUR_LINE_L, mask_sh),\ SF 146 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_LONG_LINE_ERROR, mask_sh),\ SF 147 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_SHORT_LINE_ERROR, mask_sh),\ SF 148 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_FRAME_LENGTH_ERROR, mask_sh),\ SF 149 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_CUR_LINE_R, mask_sh),\ SF 150 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_NEW_CONTENT, mask_sh),\ SF 151 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_COLOR_DEPTH, mask_sh),\ SF 152 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ_BLACK_PIXEL, mask_sh),\ SF 153 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ, mask_sh),\ SF 154 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_Y_OVERRUN, mask_sh),\ SF 155 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_C_OVERRUN, mask_sh),\ SF 156 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_ACTIVE, mask_sh),\ SF 157 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_SW_LOCKED, mask_sh),\ SF 158 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_VCE_LOCKED, mask_sh),\ SF 159 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_OVERFLOW, mask_sh),\ SF 160 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_DISABLE, mask_sh),\ SF 161 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_MODE, mask_sh),\ SF 162 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_BUFTAG, mask_sh),\ SF 163 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_NXT_BUF, mask_sh),\ SF 164 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_FIELD, mask_sh),\ SF 165 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_CUR_LINE_L, mask_sh),\ SF 166 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_LONG_LINE_ERROR, mask_sh),\ SF 167 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_SHORT_LINE_ERROR, mask_sh),\ SF 168 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_FRAME_LENGTH_ERROR, mask_sh),\ SF 169 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_CUR_LINE_R, mask_sh),\ SF 170 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_NEW_CONTENT, mask_sh),\ SF 171 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_COLOR_DEPTH, mask_sh),\ SF 172 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ_BLACK_PIXEL, mask_sh),\ SF 173 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ, mask_sh),\ SF 174 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_Y_OVERRUN, mask_sh),\ SF 175 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_C_OVERRUN, mask_sh),\ SF 176 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_ACTIVE, mask_sh),\ SF 177 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_SW_LOCKED, mask_sh),\ SF 178 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_VCE_LOCKED, mask_sh),\ SF 179 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_OVERFLOW, mask_sh),\ SF 180 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_DISABLE, mask_sh),\ SF 181 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_MODE, mask_sh),\ SF 182 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_BUFTAG, mask_sh),\ SF 183 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_NXT_BUF, mask_sh),\ SF 184 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_FIELD, mask_sh),\ SF 185 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_CUR_LINE_L, mask_sh),\ SF 186 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_LONG_LINE_ERROR, mask_sh),\ SF 187 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_SHORT_LINE_ERROR, mask_sh),\ SF 188 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_FRAME_LENGTH_ERROR, mask_sh),\ SF 189 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_CUR_LINE_R, mask_sh),\ SF 190 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_NEW_CONTENT, mask_sh),\ SF 191 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_COLOR_DEPTH, mask_sh),\ SF 192 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ_BLACK_PIXEL, mask_sh),\ SF 193 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ, mask_sh),\ SF 194 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_Y_OVERRUN, mask_sh),\ SF 195 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_C_OVERRUN, mask_sh),\ SF 196 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_ACTIVE, mask_sh),\ SF 197 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_SW_LOCKED, mask_sh),\ SF 198 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_VCE_LOCKED, mask_sh),\ SF 199 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_OVERFLOW, mask_sh),\ SF 200 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_DISABLE, mask_sh),\ SF 201 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_MODE, mask_sh),\ SF 202 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_BUFTAG, mask_sh),\ SF 203 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_NXT_BUF, mask_sh),\ SF 204 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_FIELD, mask_sh),\ SF 205 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_CUR_LINE_L, mask_sh),\ SF 206 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_LONG_LINE_ERROR, mask_sh),\ SF 207 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_SHORT_LINE_ERROR, mask_sh),\ SF 208 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_FRAME_LENGTH_ERROR, mask_sh),\ SF 209 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_CUR_LINE_R, mask_sh),\ SF 210 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_NEW_CONTENT, mask_sh),\ SF 211 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_COLOR_DEPTH, mask_sh),\ SF 212 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_TMZ_BLACK_PIXEL, mask_sh),\ SF 213 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_TMZ, mask_sh),\ SF 214 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_Y_OVERRUN, mask_sh),\ SF 215 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_C_OVERRUN, mask_sh),\ SF 216 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE, mask_sh),\ SF 217 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, mask_sh),\ SF 218 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, WM_CHANGE_ACK_FORCE_ON, mask_sh),\ SF 219 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, mask_sh),\ SF 220 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX, MCIF_WB_TEST_DEBUG_INDEX, mask_sh),\ SF 221 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_TEST_DEBUG_DATA, MCIF_WB_TEST_DEBUG_DATA, mask_sh),\ SF 222 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, mask_sh),\ SF 223 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB_BUF_1_ADDR_Y_OFFSET, mask_sh),\ SF 224 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, mask_sh),\ SF 225 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB_BUF_1_ADDR_C_OFFSET, mask_sh),\ SF 226 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, mask_sh),\ SF 227 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB_BUF_2_ADDR_Y_OFFSET, mask_sh),\ SF 228 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, mask_sh),\ SF 229 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB_BUF_2_ADDR_C_OFFSET, mask_sh),\ SF 230 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, mask_sh),\ SF 231 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB_BUF_3_ADDR_Y_OFFSET, mask_sh),\ SF 232 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, mask_sh),\ SF 233 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB_BUF_3_ADDR_C_OFFSET, mask_sh),\ SF 234 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, mask_sh),\ SF 235 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB_BUF_4_ADDR_Y_OFFSET, mask_sh),\ SF 236 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, mask_sh),\ SF 237 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB_BUF_4_ADDR_C_OFFSET, mask_sh),\ SF 238 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK_IGNORE, mask_sh),\ SF 239 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_EN, mask_sh),\ SF 240 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_ACK, mask_sh),\ SF 241 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN, mask_sh),\ SF 242 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK, mask_sh),\ SF 243 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, mask_sh),\ SF 244 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_REFRESH_WATERMARK, mask_sh),\ SF 245 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\ SF 246 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_FORCE_ON, mask_sh),\ SF 247 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_ALLOW_FOR_URGENT, mask_sh),\ SF 248 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\ SF 249 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, mask_sh),\ SF 250 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB_CLI_CLOCK_GATER_OVERRIDE, mask_sh),\ SF 251 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_WARM_UP_CNTL, MCIF_WB_PITCH_SIZE_WARMUP, mask_sh),\ SF 252 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL, DIS_REFRESH_UNDER_NBPREQ, mask_sh),\ SF 253 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL, PERFRAME_SELF_REFRESH, mask_sh),\ SF 254 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MULTI_LEVEL_QOS_CTRL, MAX_SCALED_TIME_TO_URGENT, mask_sh),\ SF 255 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_SECURITY_LEVEL, MCIF_WB_SECURITY_LEVEL, mask_sh),\ SF 256 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, mask_sh),\ SF 257 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, mask_sh),\ SF 258 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, mask_sh),\ SF 259 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, mask_sh),\ SF 260 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, mask_sh),\ SF 261 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, mask_sh),\ SF 262 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB_BUF_3_ADDR_Y_HIGH, mask_sh),\ SF 263 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB_BUF_3_ADDR_C_HIGH, mask_sh),\ SF 264 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB_BUF_4_ADDR_Y_HIGH, mask_sh),\ SF 265 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB_BUF_4_ADDR_C_HIGH, mask_sh),\ SF 266 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION, MCIF_WB_BUF_1_RESOLUTION_WIDTH, mask_sh),\ SF 267 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION, MCIF_WB_BUF_1_RESOLUTION_HEIGHT, mask_sh),\ SF 268 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION, MCIF_WB_BUF_2_RESOLUTION_WIDTH, mask_sh),\ SF 269 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION, MCIF_WB_BUF_2_RESOLUTION_HEIGHT, mask_sh),\ SF 270 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION, MCIF_WB_BUF_3_RESOLUTION_WIDTH, mask_sh),\ SF 271 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION, MCIF_WB_BUF_3_RESOLUTION_HEIGHT, mask_sh),\ SF 272 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION, MCIF_WB_BUF_4_RESOLUTION_WIDTH, mask_sh),\ SF 273 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION, MCIF_WB_BUF_4_RESOLUTION_HEIGHT, mask_sh),\ SF 274 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(WBIF0_SMU_WM_CONTROL, MCIF_WB0_WM_CHG_SEL, mask_sh),\ SF 275 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(WBIF0_SMU_WM_CONTROL, MCIF_WB0_WM_CHG_REQ, mask_sh),\ SF 276 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(WBIF0_SMU_WM_CONTROL, MCIF_WB0_WM_CHG_ACK_INT_DIS, mask_sh),\ SF 277 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(WBIF0_SMU_WM_CONTROL, MCIF_WB0_WM_CHG_ACK_INT_STATUS, mask_sh) SF 132 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\ SF 133 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\ SF 134 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\ SF 135 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\ SF 136 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\ SF 137 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\ SF 138 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\ SF 139 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\ SF 140 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\ SF 141 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\ SF 142 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ SF 143 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\ SF 144 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ SF 145 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM_RAMA_EXP_REGION_END_B, mask_sh),\ SF 146 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\ SF 147 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh),\ SF 148 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh),\ SF 149 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_B, mask_sh),\ SF 150 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\ SF 151 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh),\ SF 152 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ SF 153 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh),\ SF 154 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ SF 155 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B, MPCC_OGAM_RAMB_EXP_REGION_END_B, mask_sh),\ SF 156 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh),\ SF 157 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh),\ SF 158 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B, MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh),\ SF 159 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM_RAMB_EXP_REGION_START_B, mask_sh),\ SF 160 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh),\ SF 161 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\ SF 162 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\ SF 163 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_LUT_INDEX, MPCC_OGAM_LUT_INDEX, mask_sh),\ SF 164 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM_LUT_WRITE_EN_MASK, mask_sh),\ SF 165 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM_LUT_RAM_SEL, mask_sh),\ SF 166 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM_CONFIG_STATUS, mask_sh),\ SF 167 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_LUT_DATA, MPCC_OGAM_LUT_DATA, mask_sh),\ SF 168 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPCC_OGAM0_MPCC_OGAM_MODE, MPCC_OGAM_MODE, mask_sh),\ SF 169 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_MODE, mask_sh),\ SF 170 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MAX_R_CR, mask_sh),\ SF 171 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MIN_R_CR, mask_sh),\ SF 172 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MAX_G_Y, mask_sh),\ SF 173 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MIN_G_Y, mask_sh),\ SF 174 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\ SF 175 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh) SF 48 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_X, mask_sh),\ SF 49 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_Y, mask_sh),\ SF 50 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\ SF 51 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\ SF 52 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(OTG0_OTG_GLOBAL_CONTROL2, DIG_UPDATE_LOCATION, mask_sh),\ SF 53 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\ SF 54 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\ SF 55 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \ SF 56 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\ SF 57 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\ SF 58 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \ SF 59 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \ SF 60 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \ SF 61 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \ SF 62 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \ SF 63 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_X, mask_sh), \ SF 64 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_LINE_NUM, mask_sh),\ SF 65 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\ SF 66 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\ SF 67 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\ SF 68 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\ SF 69 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\ SF 70 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\ SF 71 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\ SF 72 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\ SF 73 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\ SF 74 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\ SF 75 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh),\ SF 76 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SF(OTG0_OTG_MANUAL_FLOW_CONTROL, MANUAL_FLOW_CONTROL, mask_sh) SF 532 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ SF 533 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ SF 54 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h SF(DCN_VM_CONTEXT0_CNTL, VM_CONTEXT0_PAGE_TABLE_DEPTH, mask_sh),\ SF 55 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h SF(DCN_VM_CONTEXT0_CNTL, VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE, mask_sh),\ SF 56 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h SF(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\ SF 57 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h SF(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\ SF 58 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h SF(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4, mask_sh),\ SF 59 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h SF(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32, mask_sh),\ SF 60 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h SF(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4, mask_sh),\ SF 61 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h SF(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32, mask_sh) SF 383 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ SF 384 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ SF 50 fs/reiserfs/procfs.c #define SFP( x ) SF( s_proc_info_data.x ) SF 102 fs/reiserfs/procfs.c SF(s_mount_state) == REISERFS_VALID_FS ? SF 118 fs/reiserfs/procfs.c SF(s_disk_reads), SF(s_disk_writes), SF(s_fix_nodes), SF 119 fs/reiserfs/procfs.c SF(s_do_balance), SF(s_unneeded_left_neighbor), SF 120 fs/reiserfs/procfs.c SF(s_good_search_by_key_reada), SF(s_bmaps), SF 121 fs/reiserfs/procfs.c SF(s_bmaps_without_search), SF(s_direct2indirect), SF 122 fs/reiserfs/procfs.c SF(s_indirect2direct), SFP(max_hash_collisions), SFP(breads), SF 73 tools/lib/traceevent/plugins/plugin_mac80211.c SF("assoc"); SP(); SF 74 tools/lib/traceevent/plugins/plugin_mac80211.c SF("aid"); SP(); SF 75 tools/lib/traceevent/plugins/plugin_mac80211.c SF("cts"); SP(); SF 76 tools/lib/traceevent/plugins/plugin_mac80211.c SF("shortpre"); SP(); SF 77 tools/lib/traceevent/plugins/plugin_mac80211.c SF("shortslot"); SP(); SF 78 tools/lib/traceevent/plugins/plugin_mac80211.c SF("dtimper"); SP(); SF 80 tools/lib/traceevent/plugins/plugin_mac80211.c SF("bcnint"); SP(); SF 83 tools/lib/traceevent/plugins/plugin_mac80211.c SF("enable_beacon"); SF 85 tools/lib/traceevent/plugins/plugin_mac80211.c SF("ht_operation_mode");