SE_RR 2519 arch/powerpc/xmon/ppc-opc.c #define SE_RR_MASK SE_RR(0x3f, 3) SE_RR 7000 arch/powerpc/xmon/ppc-opc.c {"se_mr", SE_RR(0,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, SE_RR 7001 arch/powerpc/xmon/ppc-opc.c {"se_mtar", SE_RR(0,2), SE_RR_MASK, PPCVLE, 0, {ARX, RY}}, SE_RR 7002 arch/powerpc/xmon/ppc-opc.c {"se_mfar", SE_RR(0,3), SE_RR_MASK, PPCVLE, 0, {RX, ARY}}, SE_RR 7003 arch/powerpc/xmon/ppc-opc.c {"se_add", SE_RR(1,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, SE_RR 7004 arch/powerpc/xmon/ppc-opc.c {"se_mullw", SE_RR(1,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, SE_RR 7005 arch/powerpc/xmon/ppc-opc.c {"se_sub", SE_RR(1,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, SE_RR 7006 arch/powerpc/xmon/ppc-opc.c {"se_subf", SE_RR(1,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, SE_RR 7007 arch/powerpc/xmon/ppc-opc.c {"se_cmp", SE_RR(3,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, SE_RR 7008 arch/powerpc/xmon/ppc-opc.c {"se_cmpl", SE_RR(3,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, SE_RR 7009 arch/powerpc/xmon/ppc-opc.c {"se_cmph", SE_RR(3,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, SE_RR 7010 arch/powerpc/xmon/ppc-opc.c {"se_cmphl", SE_RR(3,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, SE_RR 7068 arch/powerpc/xmon/ppc-opc.c {"se_srw", SE_RR(16,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, SE_RR 7069 arch/powerpc/xmon/ppc-opc.c {"se_sraw", SE_RR(16,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, SE_RR 7070 arch/powerpc/xmon/ppc-opc.c {"se_slw", SE_RR(16,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, SE_RR 7071 arch/powerpc/xmon/ppc-opc.c {"se_nop", SE_RR(17,0), 0xffff, PPCVLE, 0, {0}}, SE_RR 7072 arch/powerpc/xmon/ppc-opc.c {"se_or", SE_RR(17,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, SE_RR 7073 arch/powerpc/xmon/ppc-opc.c {"se_andc", SE_RR(17,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, SE_RR 7074 arch/powerpc/xmon/ppc-opc.c {"se_and", SE_RR(17,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, SE_RR 7075 arch/powerpc/xmon/ppc-opc.c {"se_and.", SE_RR(17,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},