SET_REG_BIT        53 arch/mips/include/asm/mach-pnx833x/gpio.h 		SET_REG_BIT(PNX833X_PIO_DIR, pin);
SET_REG_BIT        55 arch/mips/include/asm/mach-pnx833x/gpio.h 		SET_REG_BIT(PNX833X_PIO_DIR2, pin & 31);
SET_REG_BIT        69 arch/mips/include/asm/mach-pnx833x/gpio.h 		SET_REG_BIT(PNX833X_PIO_SEL, pin);
SET_REG_BIT        71 arch/mips/include/asm/mach-pnx833x/gpio.h 		SET_REG_BIT(PNX833X_PIO_SEL2, pin & 31);
SET_REG_BIT        88 arch/mips/include/asm/mach-pnx833x/gpio.h 			SET_REG_BIT(PNX833X_PIO_OUT, pin);
SET_REG_BIT        93 arch/mips/include/asm/mach-pnx833x/gpio.h 			SET_REG_BIT(PNX833X_PIO_OUT2, pin & 31);
SET_REG_BIT       112 arch/mips/include/asm/mach-pnx833x/gpio.h 		SET_REG_BIT(PNX833X_PIO_INT_LO, pin);
SET_REG_BIT       116 arch/mips/include/asm/mach-pnx833x/gpio.h 		SET_REG_BIT(PNX833X_PIO_INT_HI, pin);
SET_REG_BIT       120 arch/mips/include/asm/mach-pnx833x/gpio.h 		SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
SET_REG_BIT       121 arch/mips/include/asm/mach-pnx833x/gpio.h 		SET_REG_BIT(PNX833X_PIO_INT_HI, pin);
SET_REG_BIT       125 arch/mips/include/asm/mach-pnx833x/gpio.h 		SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
SET_REG_BIT       127 arch/mips/include/asm/mach-pnx833x/gpio.h 		SET_REG_BIT(PNX833X_PIO_INT_LO, pin);
SET_REG_BIT       130 arch/mips/include/asm/mach-pnx833x/gpio.h 		SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
SET_REG_BIT       131 arch/mips/include/asm/mach-pnx833x/gpio.h 		SET_REG_BIT(PNX833X_PIO_INT_HI, pin);
SET_REG_BIT       132 arch/mips/include/asm/mach-pnx833x/gpio.h 		SET_REG_BIT(PNX833X_PIO_INT_LO, pin);
SET_REG_BIT       145 arch/mips/include/asm/mach-pnx833x/gpio.h 	SET_REG_BIT(PNX833X_PIO_INT_ENABLE, pin);
SET_REG_BIT       155 arch/mips/include/asm/mach-pnx833x/gpio.h 	SET_REG_BIT(PNX833X_PIO_INT_CLEAR, pin);
SET_REG_BIT        37 drivers/net/ethernet/apm/xgene-v2/mac.c 		SET_REG_BIT(&rgmii, CFG_SPEED_125, 0);
SET_REG_BIT        44 drivers/net/ethernet/apm/xgene-v2/mac.c 		SET_REG_BIT(&rgmii, CFG_SPEED_125, 0);
SET_REG_BIT        51 drivers/net/ethernet/apm/xgene-v2/mac.c 		SET_REG_BIT(&rgmii, CFG_SPEED_125, 1);