SET_BIT_INFO      526 drivers/gpu/drm/i915/gvt/interrupt.c 	SET_BIT_INFO(irq, 0, RCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT0);
SET_BIT_INFO      527 drivers/gpu/drm/i915/gvt/interrupt.c 	SET_BIT_INFO(irq, 4, RCS_PIPE_CONTROL, INTEL_GVT_IRQ_INFO_GT0);
SET_BIT_INFO      528 drivers/gpu/drm/i915/gvt/interrupt.c 	SET_BIT_INFO(irq, 8, RCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT0);
SET_BIT_INFO      530 drivers/gpu/drm/i915/gvt/interrupt.c 	SET_BIT_INFO(irq, 16, BCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT0);
SET_BIT_INFO      531 drivers/gpu/drm/i915/gvt/interrupt.c 	SET_BIT_INFO(irq, 20, BCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT0);
SET_BIT_INFO      532 drivers/gpu/drm/i915/gvt/interrupt.c 	SET_BIT_INFO(irq, 24, BCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT0);
SET_BIT_INFO      535 drivers/gpu/drm/i915/gvt/interrupt.c 	SET_BIT_INFO(irq, 0, VCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT1);
SET_BIT_INFO      536 drivers/gpu/drm/i915/gvt/interrupt.c 	SET_BIT_INFO(irq, 4, VCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT1);
SET_BIT_INFO      537 drivers/gpu/drm/i915/gvt/interrupt.c 	SET_BIT_INFO(irq, 8, VCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT1);
SET_BIT_INFO      540 drivers/gpu/drm/i915/gvt/interrupt.c 		SET_BIT_INFO(irq, 16, VCS2_MI_USER_INTERRUPT,
SET_BIT_INFO      542 drivers/gpu/drm/i915/gvt/interrupt.c 		SET_BIT_INFO(irq, 20, VCS2_MI_FLUSH_DW,
SET_BIT_INFO      544 drivers/gpu/drm/i915/gvt/interrupt.c 		SET_BIT_INFO(irq, 24, VCS2_AS_CONTEXT_SWITCH,
SET_BIT_INFO      549 drivers/gpu/drm/i915/gvt/interrupt.c 	SET_BIT_INFO(irq, 0, VECS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT3);
SET_BIT_INFO      550 drivers/gpu/drm/i915/gvt/interrupt.c 	SET_BIT_INFO(irq, 4, VECS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT3);
SET_BIT_INFO      551 drivers/gpu/drm/i915/gvt/interrupt.c 	SET_BIT_INFO(irq, 8, VECS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT3);
SET_BIT_INFO      553 drivers/gpu/drm/i915/gvt/interrupt.c 	SET_BIT_INFO(irq, 0, PIPE_A_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
SET_BIT_INFO      554 drivers/gpu/drm/i915/gvt/interrupt.c 	SET_BIT_INFO(irq, 0, PIPE_B_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
SET_BIT_INFO      555 drivers/gpu/drm/i915/gvt/interrupt.c 	SET_BIT_INFO(irq, 0, PIPE_C_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
SET_BIT_INFO      558 drivers/gpu/drm/i915/gvt/interrupt.c 	SET_BIT_INFO(irq, 0, AUX_CHANNEL_A, INTEL_GVT_IRQ_INFO_DE_PORT);
SET_BIT_INFO      559 drivers/gpu/drm/i915/gvt/interrupt.c 	SET_BIT_INFO(irq, 3, DP_A_HOTPLUG, INTEL_GVT_IRQ_INFO_DE_PORT);
SET_BIT_INFO      562 drivers/gpu/drm/i915/gvt/interrupt.c 	SET_BIT_INFO(irq, 0, GSE, INTEL_GVT_IRQ_INFO_DE_MISC);
SET_BIT_INFO      565 drivers/gpu/drm/i915/gvt/interrupt.c 	SET_BIT_INFO(irq, 17, GMBUS, INTEL_GVT_IRQ_INFO_PCH);
SET_BIT_INFO      566 drivers/gpu/drm/i915/gvt/interrupt.c 	SET_BIT_INFO(irq, 19, CRT_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
SET_BIT_INFO      567 drivers/gpu/drm/i915/gvt/interrupt.c 	SET_BIT_INFO(irq, 21, DP_B_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
SET_BIT_INFO      568 drivers/gpu/drm/i915/gvt/interrupt.c 	SET_BIT_INFO(irq, 22, DP_C_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
SET_BIT_INFO      569 drivers/gpu/drm/i915/gvt/interrupt.c 	SET_BIT_INFO(irq, 23, DP_D_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
SET_BIT_INFO      572 drivers/gpu/drm/i915/gvt/interrupt.c 		SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_PCH);
SET_BIT_INFO      573 drivers/gpu/drm/i915/gvt/interrupt.c 		SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_PCH);
SET_BIT_INFO      574 drivers/gpu/drm/i915/gvt/interrupt.c 		SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_PCH);
SET_BIT_INFO      576 drivers/gpu/drm/i915/gvt/interrupt.c 		SET_BIT_INFO(irq, 4, PRIMARY_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
SET_BIT_INFO      577 drivers/gpu/drm/i915/gvt/interrupt.c 		SET_BIT_INFO(irq, 5, SPRITE_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
SET_BIT_INFO      579 drivers/gpu/drm/i915/gvt/interrupt.c 		SET_BIT_INFO(irq, 4, PRIMARY_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
SET_BIT_INFO      580 drivers/gpu/drm/i915/gvt/interrupt.c 		SET_BIT_INFO(irq, 5, SPRITE_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
SET_BIT_INFO      582 drivers/gpu/drm/i915/gvt/interrupt.c 		SET_BIT_INFO(irq, 4, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
SET_BIT_INFO      583 drivers/gpu/drm/i915/gvt/interrupt.c 		SET_BIT_INFO(irq, 5, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
SET_BIT_INFO      585 drivers/gpu/drm/i915/gvt/interrupt.c 		SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_DE_PORT);
SET_BIT_INFO      586 drivers/gpu/drm/i915/gvt/interrupt.c 		SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_DE_PORT);
SET_BIT_INFO      587 drivers/gpu/drm/i915/gvt/interrupt.c 		SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_DE_PORT);
SET_BIT_INFO      589 drivers/gpu/drm/i915/gvt/interrupt.c 		SET_BIT_INFO(irq, 3, PRIMARY_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
SET_BIT_INFO      590 drivers/gpu/drm/i915/gvt/interrupt.c 		SET_BIT_INFO(irq, 3, PRIMARY_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
SET_BIT_INFO      591 drivers/gpu/drm/i915/gvt/interrupt.c 		SET_BIT_INFO(irq, 3, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
SET_BIT_INFO      593 drivers/gpu/drm/i915/gvt/interrupt.c 		SET_BIT_INFO(irq, 4, SPRITE_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
SET_BIT_INFO      594 drivers/gpu/drm/i915/gvt/interrupt.c 		SET_BIT_INFO(irq, 4, SPRITE_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
SET_BIT_INFO      595 drivers/gpu/drm/i915/gvt/interrupt.c 		SET_BIT_INFO(irq, 4, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
SET_BIT_INFO      599 drivers/gpu/drm/i915/gvt/interrupt.c 	SET_BIT_INFO(irq, 24, PCU_THERMAL, INTEL_GVT_IRQ_INFO_PCU);
SET_BIT_INFO      600 drivers/gpu/drm/i915/gvt/interrupt.c 	SET_BIT_INFO(irq, 25, PCU_PCODE2DRIVER_MAILBOX, INTEL_GVT_IRQ_INFO_PCU);