BASEADDR_V7M_SCB   90 arch/arm/include/asm/cachetype.h 	writel(cache_selector, BASEADDR_V7M_SCB + V7M_SCB_CTR);
BASEADDR_V7M_SCB   95 arch/arm/include/asm/cachetype.h 	return readl(BASEADDR_V7M_SCB + V7M_SCB_CCSIDR);
BASEADDR_V7M_SCB  155 arch/arm/include/asm/cputype.h 	return readl(BASEADDR_V7M_SCB + offset);
BASEADDR_V7M_SCB  199 arch/arm/include/asm/cputype.h 	return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID);
BASEADDR_V7M_SCB  204 arch/arm/include/asm/cputype.h 	return readl(BASEADDR_V7M_SCB + V7M_SCB_CTR);
BASEADDR_V7M_SCB  209 arch/arm/include/asm/cputype.h 	return readl(BASEADDR_V7M_SCB + MPU_TYPE);
BASEADDR_V7M_SCB   14 arch/arm/kernel/v7m.c 			BASEADDR_V7M_SCB + V7M_SCB_AIRCR);
BASEADDR_V7M_SCB  105 arch/arm/mm/pmsa-v7.c 	writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv7_RNR);
BASEADDR_V7M_SCB  113 arch/arm/mm/pmsa-v7.c 	u32 rsr = readl_relaxed(BASEADDR_V7M_SCB + PMSAv7_RASR) & GENMASK(15, 0);
BASEADDR_V7M_SCB  115 arch/arm/mm/pmsa-v7.c 	writel_relaxed((v << 16) | rsr, BASEADDR_V7M_SCB + PMSAv7_RASR);
BASEADDR_V7M_SCB  121 arch/arm/mm/pmsa-v7.c 	u32 racr = readl_relaxed(BASEADDR_V7M_SCB + PMSAv7_RASR) & GENMASK(31, 16);
BASEADDR_V7M_SCB  123 arch/arm/mm/pmsa-v7.c 	writel_relaxed(v | racr, BASEADDR_V7M_SCB + PMSAv7_RASR);
BASEADDR_V7M_SCB  129 arch/arm/mm/pmsa-v7.c 	writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv7_RBAR);
BASEADDR_V7M_SCB  134 arch/arm/mm/pmsa-v7.c 	return readl_relaxed(BASEADDR_V7M_SCB + PMSAv7_RBAR);
BASEADDR_V7M_SCB   53 arch/arm/mm/pmsa-v8.c 	return readl_relaxed(BASEADDR_V7M_SCB + PMSAv8_RLAR);
BASEADDR_V7M_SCB   58 arch/arm/mm/pmsa-v8.c 	return readl_relaxed(BASEADDR_V7M_SCB + PMSAv8_RBAR);
BASEADDR_V7M_SCB   63 arch/arm/mm/pmsa-v8.c 	writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv8_RNR);
BASEADDR_V7M_SCB   68 arch/arm/mm/pmsa-v8.c 	writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv8_RBAR);
BASEADDR_V7M_SCB   73 arch/arm/mm/pmsa-v8.c 	writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv8_RLAR);