BASE 411 arch/mips/include/asm/mips-boards/bonito64.h #define BONITO_PCIMEMBASECFGBASE(WIN, BASE) (((BASE)>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) BASE 537 arch/mips/kernel/traps.c ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); BASE 577 arch/mips/kernel/traps.c ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); BASE 181 arch/sparc/net/bpf_jit_comp_32.c #define emit_loadptr(BASE, STRUCT, FIELD, DEST) \ BASE 184 arch/sparc/net/bpf_jit_comp_32.c *prog++ = LDPTRI | RS1(BASE) | S13(_off) | RD(DEST); \ BASE 187 arch/sparc/net/bpf_jit_comp_32.c #define emit_load32(BASE, STRUCT, FIELD, DEST) \ BASE 190 arch/sparc/net/bpf_jit_comp_32.c *prog++ = LD32I | RS1(BASE) | S13(_off) | RD(DEST); \ BASE 193 arch/sparc/net/bpf_jit_comp_32.c #define emit_load16(BASE, STRUCT, FIELD, DEST) \ BASE 196 arch/sparc/net/bpf_jit_comp_32.c *prog++ = LD16I | RS1(BASE) | S13(_off) | RD(DEST); \ BASE 199 arch/sparc/net/bpf_jit_comp_32.c #define __emit_load8(BASE, STRUCT, FIELD, DEST) \ BASE 201 arch/sparc/net/bpf_jit_comp_32.c *prog++ = LD8I | RS1(BASE) | S13(_off) | RD(DEST); \ BASE 204 arch/sparc/net/bpf_jit_comp_32.c #define emit_load8(BASE, STRUCT, FIELD, DEST) \ BASE 206 arch/sparc/net/bpf_jit_comp_32.c __emit_load8(BASE, STRUCT, FIELD, DEST); \ BASE 237 arch/sparc/net/bpf_jit_comp_32.c #define emit_jmpl(BASE, IMM_OFF, LREG) \ BASE 238 arch/sparc/net/bpf_jit_comp_32.c *prog++ = (JMPL | IMMED | RS1(BASE) | S13(IMM_OFF) | RD(LREG)) BASE 2101 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base); BASE 2109 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base); BASE 2117 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base); BASE 52 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ BASE 138 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ BASE 142 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ BASE 704 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ BASE 37 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ BASE 41 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ BASE 46 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ BASE 170 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ BASE 174 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ BASE 179 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ BASE 798 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), BASE 38 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ BASE 42 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ BASE 46 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ BASE 50 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ BASE 40 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ BASE 44 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ BASE 48 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ BASE 52 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ BASE 424 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ BASE 428 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ BASE 432 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ BASE 436 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ BASE 440 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ BASE 1200 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), BASE 38 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ BASE 287 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ BASE 291 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ BASE 295 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ BASE 299 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ BASE 303 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ BASE 1251 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), BASE 61 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name BASE 64 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ BASE 52 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name BASE 55 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ BASE 58 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name BASE 61 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ BASE 52 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name BASE 55 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ BASE 61 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name BASE 67 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ BASE 57 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name BASE 59 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name BASE 65 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ BASE 57 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name BASE 101 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ BASE 182 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ BASE 184 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ BASE 180 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ BASE 288 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h #define VMM_MAP_ITER(VMM,PT,PTEI,PTEN,MAP,FILL,BASE,SIZE,NEXT) do { \ BASE 292 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h u64 _addr = ((BASE) + MAP->off); \ BASE 1128 drivers/hwmon/pc87360.c val = (superio_inb(sioaddr, BASE) << 8) BASE 1129 drivers/hwmon/pc87360.c | superio_inb(sioaddr, BASE + 1); BASE 43 drivers/media/pci/cobalt/cobalt-omnitek.c #define CAPABILITY_HEADER (BASE) BASE 44 drivers/media/pci/cobalt/cobalt-omnitek.c #define CAPABILITY_REGISTER (BASE + 0x04) BASE 47 drivers/media/pci/cobalt/cobalt-omnitek.c #define INTERRUPT_STATUS (BASE + 0x08) BASE 48 drivers/media/pci/cobalt/cobalt-omnitek.c #define PCI(c) (BASE + 0x40 + ((c) * 0x40)) BASE 49 drivers/media/pci/cobalt/cobalt-omnitek.c #define SIZE(c) (BASE + 0x58 + ((c) * 0x40)) BASE 50 drivers/media/pci/cobalt/cobalt-omnitek.c #define DESCRIPTOR(c) (BASE + 0x50 + ((c) * 0x40)) BASE 51 drivers/media/pci/cobalt/cobalt-omnitek.c #define CS_REG(c) (BASE + 0x60 + ((c) * 0x40)) BASE 52 drivers/media/pci/cobalt/cobalt-omnitek.c #define BYTES_TRANSFERRED(c) (BASE + 0x64 + ((c) * 0x40)) BASE 15 drivers/media/tuners/tuner-xc2028-types.h #define BASE_TYPES (BASE|F8MHZ|MTS|FM|INPUT1|INPUT2|INIT1) BASE 178 drivers/media/tuners/tuner-xc2028.c if (type & BASE) BASE 453 drivers/media/tuners/tuner-xc2028.c if (type & BASE) BASE 762 drivers/media/tuners/tuner-xc2028.c (((BASE | new_fw.type) & BASE_TYPES) == BASE 778 drivers/media/tuners/tuner-xc2028.c rc = load_firmware(fe, BASE | new_fw.type, &std0); BASE 788 drivers/media/tuners/tuner-xc2028.c rc = load_firmware(fe, BASE | INIT1 | new_fw.type, &std0); BASE 790 drivers/media/tuners/tuner-xc2028.c rc = load_firmware(fe, (BASE | INIT1 | new_fw.type) & ~F8MHZ, BASE 803 drivers/media/tuners/tuner-xc2028.c if (priv->cur_fw.type == (BASE | new_fw.type) && BASE 880 drivers/media/tuners/tuner-xc2028.c priv->cur_fw.type |= BASE; BASE 554 drivers/media/tuners/xc4000.c if (type & BASE) BASE 643 drivers/media/tuners/xc4000.c & (BASE | INIT1 | FM | DTV6 | DTV7 | DTV78 | DTV8 | SCODE)) BASE 962 drivers/media/tuners/xc4000.c if (priv->cur_fw.type & BASE) { BASE 977 drivers/media/tuners/xc4000.c rc = load_firmware(fe, BASE, &std0); BASE 986 drivers/media/tuners/xc4000.c rc = load_firmware(fe, BASE | INIT1, &std0); BASE 988 drivers/media/tuners/xc4000.c rc = load_firmware(fe, BASE | INIT1, &std0); BASE 1000 drivers/media/tuners/xc4000.c if (priv->cur_fw.type == (BASE | new_fw.type) && BASE 1072 drivers/media/tuners/xc4000.c priv->cur_fw.type |= BASE; BASE 1525 drivers/media/tuners/xc4000.c & (BASE | FM | DTV6 | DTV7 | DTV78 | DTV8)) == BASE) { BASE 1558 drivers/media/tuners/xc4000.c if (priv->cur_fw.type & BASE) BASE 1585 drivers/media/tuners/xc4000.c (priv->cur_fw.type & BASE) != 0) { BASE 1699 drivers/media/tuners/xc4000.c id = ((priv->cur_fw.type & BASE) != 0 ? BASE 885 drivers/net/ethernet/smsc/smc9194.c base_address_register = inw( ioaddr + BASE ); BASE 493 drivers/ps3/ps3av_cmd.c [PS3AV_CMD_AUDIO_FS_44K-BASE] = { 6272, 6272, 17836, 17836, 8918 }, BASE 494 drivers/ps3/ps3av_cmd.c [PS3AV_CMD_AUDIO_FS_48K-BASE] = { 6144, 6144, 11648, 11648, 5824 }, BASE 495 drivers/ps3/ps3av_cmd.c [PS3AV_CMD_AUDIO_FS_88K-BASE] = { 12544, 12544, 35672, 35672, 17836 }, BASE 496 drivers/ps3/ps3av_cmd.c [PS3AV_CMD_AUDIO_FS_96K-BASE] = { 12288, 12288, 23296, 23296, 11648 }, BASE 497 drivers/ps3/ps3av_cmd.c [PS3AV_CMD_AUDIO_FS_176K-BASE] = { 25088, 25088, 71344, 71344, 35672 }, BASE 498 drivers/ps3/ps3av_cmd.c [PS3AV_CMD_AUDIO_FS_192K-BASE] = { 24576, 24576, 46592, 46592, 23296 } BASE 540 drivers/ps3/ps3av_cmd.c ns_val = ps3av_ns_table[PS3AV_CMD_AUDIO_FS_44K-BASE][d]; BASE 130 fs/xfs/libxfs/xfs_da_btree.h #define XFS_DA_LOGOFF(BASE, ADDR) ((char *)(ADDR) - (char *)(BASE)) BASE 131 fs/xfs/libxfs/xfs_da_btree.h #define XFS_DA_LOGRANGE(BASE, ADDR, SIZE) \ BASE 132 fs/xfs/libxfs/xfs_da_btree.h (uint)(XFS_DA_LOGOFF(BASE, ADDR)), \ BASE 133 fs/xfs/libxfs/xfs_da_btree.h (uint)(XFS_DA_LOGOFF(BASE, ADDR)+(SIZE)-1) BASE 100 include/linux/zutil.h s1 %= BASE; BASE 101 include/linux/zutil.h s2 %= BASE; BASE 124 sound/soc/qcom/lpass-lpaif-reg.h #define LPAIF_DMABASE_REG(v, chan, dir) __LPAIF_DMA_REG(v, chan, dir, BASE) BASE 798 tools/testing/selftests/bpf/test_sockmap.c if (test == BASE || test == BASE_SENDPAGE) BASE 1059 tools/testing/selftests/bpf/test_sockmap.c } else if (test == BASE) { BASE 1802 tools/testing/selftests/bpf/test_sockmap.c test = BASE;