SDMA1_REGISTER_OFFSET 310 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET + SDMA1_REGISTER_OFFSET 479 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET + SDMA1_REGISTER_OFFSET 267 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET + SDMA1_REGISTER_OFFSET 463 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET + SDMA1_REGISTER_OFFSET 50 drivers/gpu/drm/amd/amdgpu/cik_sdma.c SDMA1_REGISTER_OFFSET SDMA1_REGISTER_OFFSET 889 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100); SDMA1_REGISTER_OFFSET 896 drivers/gpu/drm/amd/amdgpu/cik_sdma.c orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET); SDMA1_REGISTER_OFFSET 899 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data); SDMA1_REGISTER_OFFSET 914 drivers/gpu/drm/amd/amdgpu/cik_sdma.c orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); SDMA1_REGISTER_OFFSET 917 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); SDMA1_REGISTER_OFFSET 924 drivers/gpu/drm/amd/amdgpu/cik_sdma.c orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); SDMA1_REGISTER_OFFSET 927 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); SDMA1_REGISTER_OFFSET 1085 drivers/gpu/drm/amd/amdgpu/cik_sdma.c tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); SDMA1_REGISTER_OFFSET 1087 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); SDMA1_REGISTER_OFFSET 1138 drivers/gpu/drm/amd/amdgpu/cik_sdma.c sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); SDMA1_REGISTER_OFFSET 1140 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); SDMA1_REGISTER_OFFSET 1143 drivers/gpu/drm/amd/amdgpu/cik_sdma.c sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); SDMA1_REGISTER_OFFSET 1145 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); SDMA1_REGISTER_OFFSET 63 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c SDMA1_REGISTER_OFFSET SDMA1_REGISTER_OFFSET 978 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); SDMA1_REGISTER_OFFSET 980 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); SDMA1_REGISTER_OFFSET 1031 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); SDMA1_REGISTER_OFFSET 1033 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); SDMA1_REGISTER_OFFSET 1036 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); SDMA1_REGISTER_OFFSET 1038 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); SDMA1_REGISTER_OFFSET 77 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c SDMA1_REGISTER_OFFSET SDMA1_REGISTER_OFFSET 1365 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); SDMA1_REGISTER_OFFSET 1367 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); SDMA1_REGISTER_OFFSET 1370 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); SDMA1_REGISTER_OFFSET 1372 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); SDMA1_REGISTER_OFFSET 483 drivers/gpu/drm/amd/amdgpu/vi.c {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET}, SDMA1_REGISTER_OFFSET 175 drivers/gpu/drm/radeon/cik.c case (SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET): SDMA1_REGISTER_OFFSET 3342 drivers/gpu/drm/radeon/cik.c WREG32(SDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, gb_addr_config & 0x70); SDMA1_REGISTER_OFFSET 4828 drivers/gpu/drm/radeon/cik.c RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET)); SDMA1_REGISTER_OFFSET 4885 drivers/gpu/drm/radeon/cik.c tmp = RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET); SDMA1_REGISTER_OFFSET 4974 drivers/gpu/drm/radeon/cik.c tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET); SDMA1_REGISTER_OFFSET 4976 drivers/gpu/drm/radeon/cik.c WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp); SDMA1_REGISTER_OFFSET 5175 drivers/gpu/drm/radeon/cik.c tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET); SDMA1_REGISTER_OFFSET 5177 drivers/gpu/drm/radeon/cik.c WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp); SDMA1_REGISTER_OFFSET 5528 drivers/gpu/drm/radeon/cik.c WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA1_REGISTER_OFFSET, 0); SDMA1_REGISTER_OFFSET 5529 drivers/gpu/drm/radeon/cik.c WREG32(SDMA0_GFX_APE1_CNTL + SDMA1_REGISTER_OFFSET, 0); SDMA1_REGISTER_OFFSET 6175 drivers/gpu/drm/radeon/cik.c WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100); SDMA1_REGISTER_OFFSET 6182 drivers/gpu/drm/radeon/cik.c orig = data = RREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET); SDMA1_REGISTER_OFFSET 6185 drivers/gpu/drm/radeon/cik.c WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data); SDMA1_REGISTER_OFFSET 6200 drivers/gpu/drm/radeon/cik.c orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); SDMA1_REGISTER_OFFSET 6203 drivers/gpu/drm/radeon/cik.c WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); SDMA1_REGISTER_OFFSET 6210 drivers/gpu/drm/radeon/cik.c orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); SDMA1_REGISTER_OFFSET 6213 drivers/gpu/drm/radeon/cik.c WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); SDMA1_REGISTER_OFFSET 6880 drivers/gpu/drm/radeon/cik.c tmp = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; SDMA1_REGISTER_OFFSET 6881 drivers/gpu/drm/radeon/cik.c WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, tmp); SDMA1_REGISTER_OFFSET 7064 drivers/gpu/drm/radeon/cik.c dma_cntl1 = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; SDMA1_REGISTER_OFFSET 7235 drivers/gpu/drm/radeon/cik.c WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, dma_cntl1); SDMA1_REGISTER_OFFSET 74 drivers/gpu/drm/radeon/cik_sdma.c reg = SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET; SDMA1_REGISTER_OFFSET 98 drivers/gpu/drm/radeon/cik_sdma.c reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET; SDMA1_REGISTER_OFFSET 119 drivers/gpu/drm/radeon/cik_sdma.c reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET; SDMA1_REGISTER_OFFSET 263 drivers/gpu/drm/radeon/cik_sdma.c reg_offset = SDMA1_REGISTER_OFFSET; SDMA1_REGISTER_OFFSET 313 drivers/gpu/drm/radeon/cik_sdma.c reg_offset = SDMA1_REGISTER_OFFSET; SDMA1_REGISTER_OFFSET 345 drivers/gpu/drm/radeon/cik_sdma.c reg_offset = SDMA1_REGISTER_OFFSET; SDMA1_REGISTER_OFFSET 380 drivers/gpu/drm/radeon/cik_sdma.c reg_offset = SDMA1_REGISTER_OFFSET; SDMA1_REGISTER_OFFSET 493 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); SDMA1_REGISTER_OFFSET 495 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, le32_to_cpup(fw_data++)); SDMA1_REGISTER_OFFSET 496 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); SDMA1_REGISTER_OFFSET 509 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); SDMA1_REGISTER_OFFSET 511 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, be32_to_cpup(fw_data++)); SDMA1_REGISTER_OFFSET 512 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); SDMA1_REGISTER_OFFSET 516 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);