SDMA0_REGISTER_OFFSET   49 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 	SDMA0_REGISTER_OFFSET,
SDMA0_REGISTER_OFFSET  888 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 		WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
SDMA0_REGISTER_OFFSET  891 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 		orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
SDMA0_REGISTER_OFFSET  894 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 			WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
SDMA0_REGISTER_OFFSET  909 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 		orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
SDMA0_REGISTER_OFFSET  912 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 			WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
SDMA0_REGISTER_OFFSET  919 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 		orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
SDMA0_REGISTER_OFFSET  922 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 			WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
SDMA0_REGISTER_OFFSET 1078 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 		tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
SDMA0_REGISTER_OFFSET 1080 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 		WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
SDMA0_REGISTER_OFFSET 1122 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
SDMA0_REGISTER_OFFSET 1124 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 			WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
SDMA0_REGISTER_OFFSET 1127 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
SDMA0_REGISTER_OFFSET 1129 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 			WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
SDMA0_REGISTER_OFFSET   62 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 	SDMA0_REGISTER_OFFSET,
SDMA0_REGISTER_OFFSET  971 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 		tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
SDMA0_REGISTER_OFFSET  973 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 		WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
SDMA0_REGISTER_OFFSET 1015 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
SDMA0_REGISTER_OFFSET 1017 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 			WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
SDMA0_REGISTER_OFFSET 1020 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
SDMA0_REGISTER_OFFSET 1022 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 			WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
SDMA0_REGISTER_OFFSET   76 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 	SDMA0_REGISTER_OFFSET,
SDMA0_REGISTER_OFFSET 1349 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
SDMA0_REGISTER_OFFSET 1351 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 			WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
SDMA0_REGISTER_OFFSET 1354 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
SDMA0_REGISTER_OFFSET 1356 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 			WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
SDMA0_REGISTER_OFFSET  482 drivers/gpu/drm/amd/amdgpu/vi.c 	{mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET},
SDMA0_REGISTER_OFFSET  174 drivers/gpu/drm/radeon/cik.c 	case (SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET):
SDMA0_REGISTER_OFFSET 3341 drivers/gpu/drm/radeon/cik.c 	WREG32(SDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, gb_addr_config & 0x70);
SDMA0_REGISTER_OFFSET 4826 drivers/gpu/drm/radeon/cik.c 		RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET));
SDMA0_REGISTER_OFFSET 4880 drivers/gpu/drm/radeon/cik.c 	tmp = RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET);
SDMA0_REGISTER_OFFSET 4968 drivers/gpu/drm/radeon/cik.c 		tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);
SDMA0_REGISTER_OFFSET 4970 drivers/gpu/drm/radeon/cik.c 		WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);
SDMA0_REGISTER_OFFSET 5171 drivers/gpu/drm/radeon/cik.c 	tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);
SDMA0_REGISTER_OFFSET 5173 drivers/gpu/drm/radeon/cik.c 	WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);
SDMA0_REGISTER_OFFSET 5526 drivers/gpu/drm/radeon/cik.c 		WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA0_REGISTER_OFFSET, 0);
SDMA0_REGISTER_OFFSET 5527 drivers/gpu/drm/radeon/cik.c 		WREG32(SDMA0_GFX_APE1_CNTL + SDMA0_REGISTER_OFFSET, 0);
SDMA0_REGISTER_OFFSET 6174 drivers/gpu/drm/radeon/cik.c 		WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
SDMA0_REGISTER_OFFSET 6177 drivers/gpu/drm/radeon/cik.c 		orig = data = RREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
SDMA0_REGISTER_OFFSET 6180 drivers/gpu/drm/radeon/cik.c 			WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
SDMA0_REGISTER_OFFSET 6195 drivers/gpu/drm/radeon/cik.c 		orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
SDMA0_REGISTER_OFFSET 6198 drivers/gpu/drm/radeon/cik.c 			WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
SDMA0_REGISTER_OFFSET 6205 drivers/gpu/drm/radeon/cik.c 		orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
SDMA0_REGISTER_OFFSET 6208 drivers/gpu/drm/radeon/cik.c 			WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
SDMA0_REGISTER_OFFSET 6878 drivers/gpu/drm/radeon/cik.c 	tmp = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
SDMA0_REGISTER_OFFSET 6879 drivers/gpu/drm/radeon/cik.c 	WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, tmp);
SDMA0_REGISTER_OFFSET 7063 drivers/gpu/drm/radeon/cik.c 	dma_cntl = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
SDMA0_REGISTER_OFFSET 7234 drivers/gpu/drm/radeon/cik.c 	WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, dma_cntl);
SDMA0_REGISTER_OFFSET   72 drivers/gpu/drm/radeon/cik_sdma.c 			reg = SDMA0_GFX_RB_RPTR + SDMA0_REGISTER_OFFSET;
SDMA0_REGISTER_OFFSET   96 drivers/gpu/drm/radeon/cik_sdma.c 		reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET;
SDMA0_REGISTER_OFFSET  117 drivers/gpu/drm/radeon/cik_sdma.c 		reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET;
SDMA0_REGISTER_OFFSET  261 drivers/gpu/drm/radeon/cik_sdma.c 			reg_offset = SDMA0_REGISTER_OFFSET;
SDMA0_REGISTER_OFFSET  311 drivers/gpu/drm/radeon/cik_sdma.c 			reg_offset = SDMA0_REGISTER_OFFSET;
SDMA0_REGISTER_OFFSET  343 drivers/gpu/drm/radeon/cik_sdma.c 			reg_offset = SDMA0_REGISTER_OFFSET;
SDMA0_REGISTER_OFFSET  376 drivers/gpu/drm/radeon/cik_sdma.c 			reg_offset = SDMA0_REGISTER_OFFSET;
SDMA0_REGISTER_OFFSET  484 drivers/gpu/drm/radeon/cik_sdma.c 		WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);
SDMA0_REGISTER_OFFSET  486 drivers/gpu/drm/radeon/cik_sdma.c 			WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, le32_to_cpup(fw_data++));
SDMA0_REGISTER_OFFSET  487 drivers/gpu/drm/radeon/cik_sdma.c 		WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);
SDMA0_REGISTER_OFFSET  502 drivers/gpu/drm/radeon/cik_sdma.c 		WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);
SDMA0_REGISTER_OFFSET  504 drivers/gpu/drm/radeon/cik_sdma.c 			WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, be32_to_cpup(fw_data++));
SDMA0_REGISTER_OFFSET  505 drivers/gpu/drm/radeon/cik_sdma.c 		WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);
SDMA0_REGISTER_OFFSET  515 drivers/gpu/drm/radeon/cik_sdma.c 	WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);