SDMA0_ME_CNTL    4968 drivers/gpu/drm/radeon/cik.c 		tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);
SDMA0_ME_CNTL    4970 drivers/gpu/drm/radeon/cik.c 		WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);
SDMA0_ME_CNTL    4974 drivers/gpu/drm/radeon/cik.c 		tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);
SDMA0_ME_CNTL    4976 drivers/gpu/drm/radeon/cik.c 		WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp);
SDMA0_ME_CNTL    5171 drivers/gpu/drm/radeon/cik.c 	tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);
SDMA0_ME_CNTL    5173 drivers/gpu/drm/radeon/cik.c 	WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);
SDMA0_ME_CNTL    5175 drivers/gpu/drm/radeon/cik.c 	tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);
SDMA0_ME_CNTL    5177 drivers/gpu/drm/radeon/cik.c 	WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp);
SDMA0_ME_CNTL     346 drivers/gpu/drm/radeon/cik_sdma.c 		me_cntl = RREG32(SDMA0_ME_CNTL + reg_offset);
SDMA0_ME_CNTL     351 drivers/gpu/drm/radeon/cik_sdma.c 		WREG32(SDMA0_ME_CNTL + reg_offset, me_cntl);