SDMA0_GFX_RB_WPTR   96 drivers/gpu/drm/radeon/cik_sdma.c 		reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET;
SDMA0_GFX_RB_WPTR   98 drivers/gpu/drm/radeon/cik_sdma.c 		reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET;
SDMA0_GFX_RB_WPTR  117 drivers/gpu/drm/radeon/cik_sdma.c 		reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET;
SDMA0_GFX_RB_WPTR  119 drivers/gpu/drm/radeon/cik_sdma.c 		reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET;
SDMA0_GFX_RB_WPTR  397 drivers/gpu/drm/radeon/cik_sdma.c 		WREG32(SDMA0_GFX_RB_WPTR + reg_offset, 0);
SDMA0_GFX_RB_WPTR  412 drivers/gpu/drm/radeon/cik_sdma.c 		WREG32(SDMA0_GFX_RB_WPTR + reg_offset, ring->wptr << 2);