SDMA0_GFX_RB_CNTL  352 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
SDMA0_GFX_RB_CNTL  440 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
SDMA0_GFX_RB_CNTL  442 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
SDMA0_GFX_RB_CNTL  443 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
SDMA0_GFX_RB_CNTL  460 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
SDMA0_GFX_RB_CNTL  469 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
SDMA0_GFX_RB_CNTL  526 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
SDMA0_GFX_RB_CNTL  678 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
SDMA0_GFX_RB_CNTL  680 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
SDMA0_GFX_RB_CNTL  681 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
SDMA0_GFX_RB_CNTL  699 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
SDMA0_GFX_RB_CNTL  737 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
SDMA0_GFX_RB_CNTL  821 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
SDMA0_GFX_RB_CNTL  965 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
SDMA0_GFX_RB_CNTL  967 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
SDMA0_GFX_RB_CNTL  968 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
SDMA0_GFX_RB_CNTL 1010 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
SDMA0_GFX_RB_CNTL 1050 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
SDMA0_GFX_RB_CNTL  511 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
SDMA0_GFX_RB_CNTL  643 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
SDMA0_GFX_RB_CNTL  645 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
SDMA0_GFX_RB_CNTL  646 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
SDMA0_GFX_RB_CNTL  677 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
SDMA0_GFX_RB_CNTL  743 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
SDMA0_GFX_RB_CNTL  264 drivers/gpu/drm/radeon/cik_sdma.c 		rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset);
SDMA0_GFX_RB_CNTL  266 drivers/gpu/drm/radeon/cik_sdma.c 		WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);
SDMA0_GFX_RB_CNTL  393 drivers/gpu/drm/radeon/cik_sdma.c 		WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);
SDMA0_GFX_RB_CNTL  415 drivers/gpu/drm/radeon/cik_sdma.c 		WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABLE);