SDMA0_CNTL        379 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
SDMA0_CNTL        388 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
SDMA0_CNTL       1016 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 			sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
SDMA0_CNTL       1021 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 			sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
SDMA0_CNTL       1032 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 			sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
SDMA0_CNTL       1037 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 			sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
SDMA0_CNTL        588 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
SDMA0_CNTL        590 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
SDMA0_CNTL        599 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
SDMA0_CNTL        601 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
SDMA0_CNTL       1350 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 			sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
SDMA0_CNTL       1355 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 			sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
SDMA0_CNTL       1366 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 			sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
SDMA0_CNTL       1371 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 			sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
SDMA0_CNTL        918 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 		f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
SDMA0_CNTL       1318 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 		temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
SDMA0_CNTL       1993 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
SDMA0_CNTL        573 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
SDMA0_CNTL        716 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
SDMA0_CNTL        719 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
SDMA0_CNTL       1419 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 	sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
SDMA0_CNTL       6878 drivers/gpu/drm/radeon/cik.c 	tmp = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
SDMA0_CNTL       6879 drivers/gpu/drm/radeon/cik.c 	WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, tmp);
SDMA0_CNTL       6880 drivers/gpu/drm/radeon/cik.c 	tmp = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
SDMA0_CNTL       6881 drivers/gpu/drm/radeon/cik.c 	WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, tmp);
SDMA0_CNTL       7063 drivers/gpu/drm/radeon/cik.c 	dma_cntl = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
SDMA0_CNTL       7064 drivers/gpu/drm/radeon/cik.c 	dma_cntl1 = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
SDMA0_CNTL       7234 drivers/gpu/drm/radeon/cik.c 	WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, dma_cntl);
SDMA0_CNTL       7235 drivers/gpu/drm/radeon/cik.c 	WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, dma_cntl1);
SDMA0_CNTL        314 drivers/gpu/drm/radeon/cik_sdma.c 		value = RREG32(SDMA0_CNTL + reg_offset);
SDMA0_CNTL        319 drivers/gpu/drm/radeon/cik_sdma.c 		WREG32(SDMA0_CNTL + reg_offset, value);