BACKLIGHT_DUTY_CYCLE_MASK 98 drivers/gpu/drm/gma500/cdv_device.c u32 val = REG_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; BACKLIGHT_DUTY_CYCLE_MASK 134 drivers/gpu/drm/gma500/cdv_device.c blc_pwm_ctl = REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; BACKLIGHT_DUTY_CYCLE_MASK 170 drivers/gpu/drm/gma500/cdv_intel_lvds.c REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; BACKLIGHT_DUTY_CYCLE_MASK 177 drivers/gpu/drm/gma500/cdv_intel_lvds.c ~BACKLIGHT_DUTY_CYCLE_MASK; BACKLIGHT_DUTY_CYCLE_MASK 319 drivers/gpu/drm/gma500/cdv_intel_lvds.c BACKLIGHT_DUTY_CYCLE_MASK); BACKLIGHT_DUTY_CYCLE_MASK 164 drivers/gpu/drm/gma500/oaktrail_lvds.c BACKLIGHT_DUTY_CYCLE_MASK); BACKLIGHT_DUTY_CYCLE_MASK 189 drivers/gpu/drm/gma500/psb_intel_lvds.c blc_pwm_ctl &= ~BACKLIGHT_DUTY_CYCLE_MASK; BACKLIGHT_DUTY_CYCLE_MASK 198 drivers/gpu/drm/gma500/psb_intel_lvds.c ~BACKLIGHT_DUTY_CYCLE_MASK; BACKLIGHT_DUTY_CYCLE_MASK 273 drivers/gpu/drm/gma500/psb_intel_lvds.c BACKLIGHT_DUTY_CYCLE_MASK); BACKLIGHT_DUTY_CYCLE_MASK 435 drivers/gpu/drm/gma500/psb_intel_lvds.c BACKLIGHT_DUTY_CYCLE_MASK); BACKLIGHT_DUTY_CYCLE_MASK 540 drivers/gpu/drm/i915/display/intel_panel.c return I915_READ(BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK; BACKLIGHT_DUTY_CYCLE_MASK 547 drivers/gpu/drm/i915/display/intel_panel.c return I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; BACKLIGHT_DUTY_CYCLE_MASK 556 drivers/gpu/drm/i915/display/intel_panel.c val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; BACKLIGHT_DUTY_CYCLE_MASK 575 drivers/gpu/drm/i915/display/intel_panel.c return I915_READ(VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK; BACKLIGHT_DUTY_CYCLE_MASK 608 drivers/gpu/drm/i915/display/intel_panel.c u32 val = I915_READ(BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK; BACKLIGHT_DUTY_CYCLE_MASK 618 drivers/gpu/drm/i915/display/intel_panel.c tmp = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; BACKLIGHT_DUTY_CYCLE_MASK 640 drivers/gpu/drm/i915/display/intel_panel.c mask = BACKLIGHT_DUTY_CYCLE_MASK; BACKLIGHT_DUTY_CYCLE_MASK 657 drivers/gpu/drm/i915/display/intel_panel.c tmp = I915_READ(VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK;