SDCC_HC_REG_DDR_CONFIG  124 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c 		rgmii_readl(ethqos, SDCC_HC_REG_DDR_CONFIG));
SDCC_HC_REG_DDR_CONFIG  173 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c 	{ .offset = SDCC_HC_REG_DDR_CONFIG,	.value = 0x00000000 },
SDCC_HC_REG_DDR_CONFIG  294 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c 			      57, SDCC_HC_REG_DDR_CONFIG);
SDCC_HC_REG_DDR_CONFIG  297 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c 			      SDCC_HC_REG_DDR_CONFIG);
SDCC_HC_REG_DDR_CONFIG  325 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c 			      (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG);
SDCC_HC_REG_DDR_CONFIG  328 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c 			      SDCC_HC_REG_DDR_CONFIG);
SDCC_HC_REG_DDR_CONFIG  331 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c 			      SDCC_HC_REG_DDR_CONFIG);
SDCC_HC_REG_DDR_CONFIG  359 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c 			      (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG);
SDCC_HC_REG_DDR_CONFIG  362 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c 			      SDCC_HC_REG_DDR_CONFIG);
SDCC_HC_REG_DDR_CONFIG  365 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c 			      SDCC_HC_REG_DDR_CONFIG);